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公开(公告)号：US08898246B2
公开(公告)日：2014-11-25
申请号：US10902341
申请日：2004-07-29
申请人： Gary Belgrave Gostin , Larry N. McMahan , Michael A. Schroeder , Craig W. Warner , Richard W. Adkisson , Huai-Ter Victor Chong , David M. Binford , Mark Edward Shaw , Joe P. Cowan , Thierry Fevrier , Arad Rostampour
发明人： Gary Belgrave Gostin , Larry N. McMahan , Michael A. Schroeder , Craig W. Warner , Richard W. Adkisson , Huai-Ter Victor Chong , David M. Binford , Mark Edward Shaw , Joe P. Cowan , Thierry Fevrier , Arad Rostampour
IPC分类号： G06F15/16 , G06F9/50 , G06F9/54 , G06F15/167
CPC分类号： G06F9/5077 , G06F9/544 , G06F15/167
摘要： A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.
摘要翻译： 公开了一种具有分区的计算设备和分区之间的通信方法，其中至少一个分区包括：至少一个寄存器，其基本上总是可被其他分区访问并且能够定义地址区域; 至少一个地址区域，其可以由其他分区访问并且能够由所述至少一个寄存器定义; 以及除了其他分区不可访问的至少一个可访问地址区域以外的地址区域。 一种处理中断的方法，包括接收中断，根据其来源评估中断的起始点，接受，拒绝或进一步评估中断，当进一步评估中断时，根据其中的内容接受或拒绝中断，以及转发 接受的中断但不拒绝对目标处理器的中断，并且还公开了执行该方法的设备。
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公开(公告)号：US07724758B2
公开(公告)日：2010-05-25
申请号：US10756438
申请日：2004-01-12
IPC分类号： H04L12/28
CPC分类号： H04L47/6265 , H04L47/15 , H04L47/50 , H04L49/30
摘要： Transactions are received through at least two input channels, each transaction comprising one or more data packets. The data packets are placed in a single data queue. When a first transaction received through one input channel comprises more than one data packet, a data packet of a second transaction received through another input channel is permitted to be placed in the single data queue between data packets of the first transaction. A block of space in a data output queue is assigned to each transaction. Each data packet is placed in the block assigned to its transaction.
摘要翻译： 通过至少两个输入通道接收事务，每个事务包括一个或多个数据分组。 数据包被放置在单个数据队列中。 当通过一个输入通道接收到的第一事务包括多于一个数据分组时，允许通过另一个输入通道接收的第二事务的数据分组被放置在第一事务的数据分组之间的单个数据队列中。 数据输出队列中的一个空格块被分配给每个事务。 每个数据包都被放置在分配给它的事务的块中。
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3.发明授权Data delivery based on a select data delivery performance parameter in a data processing system 失效基于数据处理系统中的选择数据传送性能参数的数据传送公开(公告)号：US07457888B2
公开(公告)日：2008-11-25
申请号：US10756448
申请日：2004-01-12
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： Delivering data from a data input to a data output within a system includes selecting a system performance parameter to be optimized, receiving at the data input a sequence of discrete data words, determining an optimum mode of delivery of the data words to the data output so as to optimize the selected performance parameter, and delivering the data words from the data input to the data output in the determined optimum mode. The optimum mode of delivery may include at least one of an optimum time and sequence of delivery of the data words.
摘要翻译： 将数据从数据输入传送到系统内的数据输出包括选择要优化的系统性能参数，在数据输入处接收一系列离散数据字，确定将数据字传送到数据输出的最佳方式， 以优化所选择的性能参数，并且以确定的最佳模式将数据字从数据输入传送到数据输出。 最佳递送方式可以包括数据字的最佳时间和递送顺序中的至少一个。
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4.发明授权System and method for effectuating the transfer of data blocks including a header block across a clock boundary 有权用于在时钟边界上实现包括报头块的数据块的传送的系统和方法公开(公告)号：US07623482B2
公开(公告)日：2009-11-24
申请号：US10625291
申请日：2003-07-23
IPC分类号： H04B7/212
摘要： A system and method for effectuating the transfer of data blocks including a header block across a clock boundary between a first clock domain and a second clock domain. In one embodiment, a first circuit portion provides the data blocks including the header block to a second circuit portion. Control logic associated with the second circuit portion is operable to process the header block and generate in response to the header block a hint signal which is transferred via a synchronizer at least one data cycle prior to the transfer of the data blocks to a third circuit portion disposed in the second clock domain. A control block associated with the third circuit portion operates responsive to the hint signal to generate data transfer control signals for controlling the third circuit portion in order to control output of the data blocks in a particular ordered grouping.
摘要翻译： 一种用于在第一时钟域和第二时钟域之间的时钟边界上实现包括报头块的数据块的传送的系统和方法。 在一个实施例中，第一电路部分将包括标题块的数据块提供给第二电路部分。 与第二电路部分相关联的控制逻辑可操作以处理报头块，并且响应于报头块生成在经由数据块传送到第三电路部分之前经由同步器传送的至少一个数据周期的提示信号 放置在第二个时钟域。 与第三电路部分相关联的控制块响应于提示信号而操作，以产生用于控制第三电路部分的数据传输控制信号，以便控制特定有序分组中的数据块的输出。
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5.发明授权System and method for effectuating the transfer of data blocks across a clock boundary 失效用于实现跨时钟边界传输数据块的系统和方法公开(公告)号：US07480357B2
公开(公告)日：2009-01-20
申请号：US10625365
申请日：2003-07-23
IPC分类号： H04L7/00
CPC分类号： G06F5/06 , H04L7/0012 , H04L7/005
摘要： A system and method for effectuating the transfer of data blocks having intervals across a clock boundary between a first clock domain and a second clock domain. A first circuit portion provides the data blocks to a second circuit portion. A synchronizer controller disposed between the first and second clock domains provides at least one dead cycle control signal to the second circuit portion, which is indicative of the location of at least one dead cycle between the first and second clock signals. Control logic associated with the second circuit portion generates data transfer control signals responsive to the at least one dead cycle control signal in order to control the second circuit portion so that the data blocks may be transmitted as contiguous data blocks relative to the at least one dead cycle.
摘要翻译： 一种用于实现在第一时钟域和第二时钟域之间跨时钟边界具有间隔的数据块的传送的系统和方法。 第一电路部分将数据块提供给第二电路部分。 设置在第一和第二时钟域之间的同步器控制器向第二电路部分提供至少一个死循环控制信号，其指示第一和第二时钟信号之间的至少一个死循环的位置。 与第二电路部分相关联的控制逻辑响应于至少一个死循环控制信号产生数据传输控制信号，以便控制第二电路部分，使得数据块可相对于至少一个死区 周期。
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6.发明授权公开(公告)号：US07774562B2
公开(公告)日：2010-08-10
申请号：US10944524
申请日：2004-09-17
IPC分类号： G06F13/36
CPC分类号： G06F12/0813 , G06F12/0817 , G06F2212/2542
摘要： A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.
摘要翻译： 一种在多处理器系统的第一单元中操作中央高速缓存控制器（“CCC”）的方法，包括多个单元，每个单元包括全局共享存储器（“GSM”），其中第一单元被布置在第一分区中并且CCC被连接 到第一小区的多个CPU。 在一个实施例中，该方法包括响应来自CPU之一的新的事务请求，在事务表中记录事务; 确定与发送所述交易的单元对应的超时映射中的身份标识是否被设置; 并且响应于所设置的超时映射中的相应身份标识，立即向请求该事务的一个CPU返回特殊错误。
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公开(公告)号：US07002376B2
公开(公告)日：2006-02-21
申请号：US11034152
申请日：2005-01-12
申请人： Richard W. Adkisson
发明人： Richard W. Adkisson
IPC分类号： H03D13/00
摘要： A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain that is clocked with a first clock signal and second circuitry disposed in a second clock domain that is clocked with a second clock signal. The phase detector includes means for sampling the second clock signal with the first clock signal to generate a sampled clock signal. By tracking movement in a predetermined transition in the sampled clock signal, the phase detector is operable to determine the phase difference between the first and second clock signals.
摘要翻译： 可编程时钟同步器中的相位检测器，用于在布置在与第一时钟信号同步的第一时钟域中的第一电路之间实现数据传输，以及设置在第二时钟域中的第二电路的第二时钟信号。 相位检测器包括用第一时钟信号对第二时钟信号进行采样以产生采样的时钟信号的装置。 通过跟踪在采样的时钟信号中的预定转变中的移动，相位检测器可操作以确定第一和第二时钟信号之间的相位差。
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公开(公告)号：US06786760B1
公开(公告)日：2004-09-07
申请号：US10420577
申请日：2003-04-21
IPC分类号： H01R300
CPC分类号： H05K7/1092
摘要： An embodiment of this invention provides a system and method for indicating the orientation of a packaged IC in a socket. An LED is physically mounted to a socket. One lead of the LED is electrically connected to a positive voltage through a socket hole on the socket. When the orientation of the IC package in the socket is correct, the other lead of the LED is connected to a ground path on the packaged IC. As a result, the LED is activated indicating the orientation of the packaged IC is correct.
摘要翻译： 本发明的实施例提供了一种用于指示封装IC在插座中的取向的系统和方法。 LED物理安装到插座。 LED的一个引线通过插座上的插座孔电连接到正电压。 当插座中的IC封装的方向正确时，LED的另一引线连接到封装IC上的接地路径。 结果，LED被激活，表示封装IC的方向是正确的。
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9.发明授权Circuits, systems and methods for preventing queue overflow in data processing systems 失效用于防止数据处理系统中的队列溢出的电路，系统和方法
公开(公告)号：US5590304A
公开(公告)日：1996-12-31
申请号：US258761
申请日：1994-06-13
申请人： Richard W. Adkisson
发明人： Richard W. Adkisson
CPC分类号： G06F5/06 , G06F13/1642
摘要： A processing system is provided which includes circuitry for generating memory requests at a first clock rate. Input queuing circuitry which includes at least one queue receives the memory requests from the circuitry at the first clock rate and outputs such memory requests at a second clock rate. A memory system stores and retrieves data in response to the memory requests, the memory system outputting data in response to read requests received from input queuing circuitry. An output queue is provided which receives data output from memory at the second clock rate and outputs such data at the first clock rate. Queuing control circuitry is provided which prevents overflow of output queue by controlling the number of memory requests sent in bursts from the input queuing system to the memory system and by controlling the wait time between such bursts.
摘要翻译： 提供了一种处理系统，其包括用于以第一时钟速率产生存储器请求的电路。 包括至少一个队列的输入排队电路以第一时钟速率从电路接收存储器请求，并以第二时钟速率输出这样的存储器请求。 存储器系统响应于存储器请求存储和检索数据，存储器系统响应于从输入排队电路接收的读取请求而输出数据。 提供输出队列，其以第二时钟速率接收从存储器输出的数据，并以第一时钟速率输出这样的数据。 提供了排队控制电路，其通过控制从输入排队系统到存储器系统的脉冲串中发送的存储器请求的数量并通过控制这种脉冲串之间的等待时间来防止输出队列的溢出。
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公开(公告)号：US07424397B2
公开(公告)日：2008-09-09
申请号：US10635083
申请日：2003-08-06
申请人： Richard W. Adkisson , Tyler Johnson
发明人： Richard W. Adkisson , Tyler Johnson
CPC分类号： G06F11/348 , G06F11/3409 , G06F11/349 , G06F2201/86 , G06F2201/88
摘要： In one embodiment, the invention is directed to a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The GPPC includes an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value, wherein the AND/OR circuit activates the increment signal responsive to a selected combination of bits of an events signal being set.
摘要翻译： 在一个实施例中，本发明涉及连接到承载调试数据的总线的通用性能计数器（“GPPC”）。 GPPC包括连接的AND / OR电路，用于接收调试数据; 一个计数器电路，连接成从AND / OR电路接收一个增量信号，该增量信号在被激活时使计数器电路递增计数; 以及比较电路，用于响应于与比较值具有第一关系的所述调试数据的选定块来激活与所述AND / OR电路的匹配/门限信号，其中所述AND / OR电路响应于所选择的组合来激活所述增量信号 设置事件信号的位。
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