公开(公告)号：US07002376B2

公开(公告)日：2006-02-21

申请号：US11034152

申请日：2005-01-12

申请人： Richard W. Adkisson

发明人： Richard W. Adkisson

IPC分类号： H03D13/00

CPC分类号： G06F1/12 ,  G06F1/10

摘要： A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain that is clocked with a first clock signal and second circuitry disposed in a second clock domain that is clocked with a second clock signal. The phase detector includes means for sampling the second clock signal with the first clock signal to generate a sampled clock signal. By tracking movement in a predetermined transition in the sampled clock signal, the phase detector is operable to determine the phase difference between the first and second clock signals.

摘要翻译： 可编程时钟同步器中的相位检测器，用于在布置在与第一时钟信号同步的第一时钟域中的第一电路之间实现数据传输，以及设置在第二时钟域中的第二电路的第二时钟信号。 相位检测器包括用第一时钟信号对第二时钟信号进行采样以产生采样的时钟信号的装置。 通过跟踪在采样的时钟信号中的预定转变中的移动，相位检测器可操作以确定第一和第二时钟信号之间的相位差。

公开(公告)号：US06786760B1

公开(公告)日：2004-09-07

申请号：US10420577

申请日：2003-04-21

申请人： John A. Benavides ,  Richard W. Adkisson

发明人： John A. Benavides ,  Richard W. Adkisson

IPC分类号： H01R300

CPC分类号： H05K7/1092

摘要： An embodiment of this invention provides a system and method for indicating the orientation of a packaged IC in a socket. An LED is physically mounted to a socket. One lead of the LED is electrically connected to a positive voltage through a socket hole on the socket. When the orientation of the IC package in the socket is correct, the other lead of the LED is connected to a ground path on the packaged IC. As a result, the LED is activated indicating the orientation of the packaged IC is correct.

摘要翻译： 本发明的实施例提供了一种用于指示封装IC在插座中的取向的系统和方法。 LED物理安装到插座。 LED的一个引线通过插座上的插座孔电连接到正电压。 当插座中的IC封装的方向正确时，LED的另一引线连接到封装IC上的接地路径。 结果，LED被激活，表示封装IC的方向是正确的。

公开(公告)号：US5590304A

公开(公告)日：1996-12-31

申请号：US258761

申请日：1994-06-13

申请人： Richard W. Adkisson

发明人： Richard W. Adkisson

IPC分类号： G06F5/06 ,  G06F13/16

CPC分类号： G06F5/06 ,  G06F13/1642

摘要： A processing system is provided which includes circuitry for generating memory requests at a first clock rate. Input queuing circuitry which includes at least one queue receives the memory requests from the circuitry at the first clock rate and outputs such memory requests at a second clock rate. A memory system stores and retrieves data in response to the memory requests, the memory system outputting data in response to read requests received from input queuing circuitry. An output queue is provided which receives data output from memory at the second clock rate and outputs such data at the first clock rate. Queuing control circuitry is provided which prevents overflow of output queue by controlling the number of memory requests sent in bursts from the input queuing system to the memory system and by controlling the wait time between such bursts.

摘要翻译： 提供了一种处理系统，其包括用于以第一时钟速率产生存储器请求的电路。 包括至少一个队列的输入排队电路以第一时钟速率从电路接收存储器请求，并以第二时钟速率输出这样的存储器请求。 存储器系统响应于存储器请求存储和检索数据，存储器系统响应于从输入排队电路接收的读取请求而输出数据。 提供输出队列，其以第二时钟速率接收从存储器输出的数据，并以第一时钟速率输出这样的数据。 提供了排队控制电路，其通过控制从输入排队系统到存储器系统的脉冲串中发送的存储器请求的数量并通过控制这种脉冲串之间的等待时间来防止输出队列的溢出。

公开(公告)号：US08898246B2

公开(公告)日：2014-11-25

申请号：US10902341

申请日：2004-07-29

申请人： Gary Belgrave Gostin ,  Larry N. McMahan ,  Michael A. Schroeder ,  Craig W. Warner ,  Richard W. Adkisson ,  Huai-Ter Victor Chong ,  David M. Binford ,  Mark Edward Shaw ,  Joe P. Cowan ,  Thierry Fevrier ,  Arad Rostampour

发明人： Gary Belgrave Gostin ,  Larry N. McMahan ,  Michael A. Schroeder ,  Craig W. Warner ,  Richard W. Adkisson ,  Huai-Ter Victor Chong ,  David M. Binford ,  Mark Edward Shaw ,  Joe P. Cowan ,  Thierry Fevrier ,  Arad Rostampour

IPC分类号： G06F15/16 ,  G06F9/50 ,  G06F9/54 ,  G06F15/167

CPC分类号： G06F9/5077 ,  G06F9/544 ,  G06F15/167

摘要： A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

摘要翻译： 公开了一种具有分区的计算设备和分区之间的通信方法，其中至少一个分区包括：至少一个寄存器，其基本上总是可被其他分区访问并且能够定义地址区域; 至少一个地址区域，其可以由其他分区访问并且能够由所述至少一个寄存器定义; 以及除了其他分区不可访问的至少一个可访问地址区域以外的地址区域。 一种处理中断的方法，包括接收中断，根据其来源评估中断的起始点，接受，拒绝或进一步评估中断，当进一步评估中断时，根据其中的内容接受或拒绝中断，以及转发 接受的中断但不拒绝对目标处理器的中断，并且还公开了执行该方法的设备。

公开(公告)号：US07424397B2

公开(公告)日：2008-09-09

申请号：US10635083

申请日：2003-08-06

申请人： Richard W. Adkisson ,  Tyler Johnson

发明人： Richard W. Adkisson ,  Tyler Johnson

IPC分类号： G06F11/30 ,  G06F11/00

CPC分类号： G06F11/348 ,  G06F11/3409 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88

摘要： In one embodiment, the invention is directed to a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The GPPC includes an AND/OR circuit connected to receive the debug data; a counter circuit connected to receive from the AND/OR circuit an increment signal that, when activated, causes the counter circuit to increment a count; and a compare circuit for activating a match/threshold signal to the AND/OR circuit responsive to a selected block of the debug data having a first relationship to a compare value, wherein the AND/OR circuit activates the increment signal responsive to a selected combination of bits of an events signal being set.

摘要翻译： 在一个实施例中，本发明涉及连接到承载调试数据的总线的通用性能计数器（“GPPC”）。 GPPC包括连接的AND / OR电路，用于接收调试数据; 一个计数器电路，连接成从AND / OR电路接收一个增量信号，该增量信号在被激活时使计数器电路递增计数; 以及比较电路，用于响应于与比较值具有第一关系的所述调试数据的选定块来激活与所述AND / OR电路的匹配/门限信号，其中所述AND / OR电路响应于所选择的组合来激活所述增量信号 设置事件信号的位。

公开(公告)号：US07340631B2

公开(公告)日：2008-03-04

申请号：US10897729

申请日：2004-07-23

申请人： Richard W. Adkisson

发明人： Richard W. Adkisson

IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC分类号： G06F1/12

摘要： A drift-tolerant sync generation circuit and sync generation method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. A sync circuit portion, responsive to a valid edge signal indicative of coincident edges between the first and second clock signals, is operable to generate based upon the ratio a start sync signal substantially centered around the coincident edges. A first sync generator, responsive to the start sync signal, is operable to generate synchronization pulses in the first clock domain. A second sync generator, responsive to the start sync signal, is operable to generate synchronization pulses in the second clock domain.

摘要翻译： 一种用于在时钟同步器中可操作的同步脉冲发生器的漂移容限同步产生电路和同步产生方法，其实现了布置在第一时钟域中的第一电路和第二时钟域内的第二电路之间的数据传输。 第一时钟域可与第一时钟信号一起工作，第二时钟域可与第二时钟信号一起工作。 响应于指示第一和第二时钟信号之间的重合边缘的有效边沿信号的同步电路部分可操作以基于大致以重合边缘为中心的开始同步信号的比率而产生。 响应于起始同步信号的第一同步发生器可操作以在第一时钟域中产生同步脉冲。 响应于起始同步信号的第二同步发生器可操作以在第二时钟域中产生同步脉冲。

公开(公告)号：US07194650B2

公开(公告)日：2007-03-20

申请号：US10629989

申请日：2003-07-30

申请人： Richard W. Adkisson

发明人： Richard W. Adkisson

IPC分类号： G06F13/42 ,  G06F5/06 ,  H04L7/04

CPC分类号： G06F1/12

摘要： A system and method for coordinating synchronizer controllers disposed in different clock domains, e.g., a core clock domain and a bus clock domain, wherein a clock synchronizer arrangement is employed for effectuating data transfer across a clock boundary therebetween. A bus clock synchronizer controller operable in the bus clock domain includes circuitry for generating a set of inter-controller clock relationship control signals, which are provided to a core clock synchronizer controller. Responsive to the inter-controller clock relationship control signals, circuitry in the core clock synchronizer controller is operable to synchronize the core clock signal's cycle and sequence information relative to the bus clock signal.

摘要翻译： 用于协调布置在不同时钟域（例如核心时钟域和总线时钟域）中的同步器控制器的系统和方法，其中使用时钟同步器装置来实现其间的时钟边界的数据传输。 在总线时钟域中可操作的总线时钟同步器控制器包括用于产生提供给核心时钟同步器控制器的一组控制器间时钟关系控制信号的电路。 响应于控制器间时钟关系控制信号，核心时钟同步器控制器中的电路可操作以使核心时钟信号的周期和序列信息相对于总线时钟信号同步。

公开(公告)号：US07119582B2

公开(公告)日：2006-10-10

申请号：US10898693

申请日：2004-07-23

申请人： Richard W. Adkisson

发明人： Richard W. Adkisson

IPC分类号： G01R25/00

CPC分类号： H04L7/02 ,  G01R25/005 ,  G01R25/02 ,  H04L7/0337

摘要： A phase detector and phase detection method for a sync pulse generator operable in a clock synchronizer that effectuates data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. The first clock domain is operable with a first clock signal and the second clock domain is operable with a second clock signal. At least one first flip flop is operable to sample the first clock signal with a rising edge of the second clock signal and at least one second flip flop is operable to sample the first clock signal with a falling edge of the second clock signal. The sampling produces transitions indicative of the coincident rising edges between the first and second signals.

摘要翻译： 一种在时钟同步器中可操作的同步脉冲发生器的相位检测器和相位检测方法，其实现了布置在第一时钟域中的第一电路和设置在第二时钟域中的第二电路之间的数据传输。 第一时钟域可与第一时钟信号一起工作，第二时钟域可与第二时钟信号一起工作。 至少一个第一触发器可操作以用第二时钟信号的上升沿对第一时钟信号进行采样，并且至少一个第二触发器可操作以用第二时钟信号的下降沿对第一时钟信号进行采样。 采样产生指示第一和第二信号之间重合的上升沿的转换。

公开(公告)号：US06996654B2

公开(公告)日：2006-02-07

申请号：US10434657

申请日：2003-05-09

申请人： Richard W. Adkisson ,  Christopher Alan Greer

发明人： Richard W. Adkisson ,  Christopher Alan Greer

IPC分类号： G06F13/36

CPC分类号： G06F13/405

摘要： Systems and methods generate transaction identifiers. A plurality of available transaction identifiers are generated for use in identifying future transactions from a first bus. A new transaction identifier is generated upon receipt of each received transaction from the first bus. One of the available transaction identifiers is assigned to each received transaction prior to generation of the new transaction identifier so that the received transaction communicated on a second bus is identified by the one transaction identifier.

摘要翻译： 系统和方法生成事务标识符。 生成多个可用事务标识符用于识别来自第一总线的未来事务。 在从第一总线接收到每个接收到的事务时，生成新的事务标识符。 在生成新的事务标识符之前，将可用事务标识符中的一个分配给每个接收到的事务，使得在第二总线上传送的接收到的事务被一个事务标识符标识。

公开(公告)号：US07724758B2

公开(公告)日：2010-05-25

申请号：US10756438

申请日：2004-01-12

申请人： Huai-Ter Victor Chong ,  Craig W. Warner ,  Richard W. Adkisson

发明人： Huai-Ter Victor Chong ,  Craig W. Warner ,  Richard W. Adkisson

IPC分类号： H04L12/28

CPC分类号： H04L47/6265 ,  H04L47/15 ,  H04L47/50 ,  H04L49/30

摘要： Transactions are received through at least two input channels, each transaction comprising one or more data packets. The data packets are placed in a single data queue. When a first transaction received through one input channel comprises more than one data packet, a data packet of a second transaction received through another input channel is permitted to be placed in the single data queue between data packets of the first transaction. A block of space in a data output queue is assigned to each transaction. Each data packet is placed in the block assigned to its transaction.

摘要翻译： 通过至少两个输入通道接收事务，每个事务包括一个或多个数据分组。 数据包被放置在单个数据队列中。 当通过一个输入通道接收到的第一事务包括多于一个数据分组时，允许通过另一个输入通道接收的第二事务的数据分组被放置在第一事务的数据分组之间的单个数据队列中。 数据输出队列中的一个空格块被分配给每个事务。 每个数据包都被放置在分配给它的事务的块中。