公开(公告)号：US20230269862A1

公开(公告)日：2023-08-24

申请号：US18308267

申请日：2023-04-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wenliang Li ,  Yongwei Chen ,  Xusheng Liu ,  Zhong Yan ,  Zewen Wang

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0225 ,  H05K1/116 ,  H05K2201/09609 ,  H05K2201/096

Abstract: A printed circuit board includes a plurality of layer structures disposed in a stacked manner, and the printed circuit board has a disposing face. A differential pair unit and a shielding structure for shielding the differential pair unit are disposed on the disposing face. The differential pair unit includes two signal via holes, each signal via hole passes through the plurality of layer structures, and an anti-pad corresponding to each signal via hole is disposed on a ground layer through which the signal via hole passes. A part of metal of a ground layer is spaced between two anti-pads. Each signal corresponds to one anti-pad, and a ground layer is spaced between anti-pads.

公开(公告)号：US11624780B2

公开(公告)日：2023-04-11

申请号：US16918762

申请日：2020-07-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Gang Zhao ,  Howard David ,  Xusheng Liu ,  Yongyao Li

IPC: G11C29/00 ,  G01R31/317 ,  G11C29/02 ,  G11C29/56

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

公开(公告)号：US12032018B2

公开(公告)日：2024-07-09

申请号：US18298305

申请日：2023-04-10

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Gang Zhao ,  Howard David ,  Xusheng Liu ,  Yongyao Li

IPC: G06F11/00 ,  G01R31/317 ,  G11C29/02 ,  G11C29/56

CPC classification number: G01R31/3171 ,  G01R31/31709 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/56008 ,  G11C29/56012 ,  G11C2029/5602

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

公开(公告)号：US20230324457A1

公开(公告)日：2023-10-12

申请号：US18298305

申请日：2023-04-10

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Gang Zhao ,  Howard David ,  Xusheng Liu ,  Yongyao Li

IPC: G01R31/317 ,  G11C29/02 ,  G11C29/56

CPC classification number: G01R31/3171 ,  G11C29/022 ,  G11C29/023 ,  G11C29/56008 ,  G11C29/56012 ,  G01R31/31709 ,  G11C29/028 ,  G11C2029/5602

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

公开(公告)号：US12058808B2

公开(公告)日：2024-08-06

申请号：US17689318

申请日：2022-03-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wenliang Li ,  Zewen Wang ,  Xusheng Liu ,  Ertang Xie ,  Zhong Yan ,  Wang Xiong

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0222 ,  H05K1/115 ,  H05K2201/0338

Abstract: A printed circuit board includes a connector insertion area including many rows of crimping holes, each row of crimping holes includes at least two pairs of signal crimping holes (SCHs), and each pair of SCHs includes two SCHs. In a row arrangement direction of the crimping holes, at least one ground crimping hole (GCH) is arranged on either side of each pair of SCHs. A depth of the GCH is greater than or equal to a depth of the SCH, the GCH includes a main hole and a shielding component on at least one side of the main hole, a part of a side wall of the main hole is a part of a side wall of the shielding component, and a sum of lengths of the main hole and the shielding component in a first direction is greater than a length of the SCHs in the first direction.

公开(公告)号：US20220192007A1

公开(公告)日：2022-06-16

申请号：US17689318

申请日：2022-03-08

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wenliang Li ,  Zewen Wang ,  Xusheng Liu ,  Ertang Xie ,  Zhong Yan ,  Wang Xiong

IPC: H05K1/02 ,  H05K1/11

Abstract: A printed circuit board includes a connector insertion area including many rows of crimping holes, each row of crimping holes includes at least two pairs of signal crimping holes (SCHs), and each pair of SCHs includes two SCHs. In a row arrangement direction of the crimping holes, at least one ground crimping hole (GCH) is arranged on either side of each pair of SCHs. A depth of the GCH is greater than or equal to a depth of the SCH, the GCH includes a main hole and a shielding component on at least one side of the main hole, a part of a side wall of the main hole is a part of a side wall of the shielding component, and a sum of lengths of the main hole and the shielding component in a first direction is greater than a length of the SCHs in the first direction.

公开(公告)号：US20200333396A1

公开(公告)日：2020-10-22

申请号：US16918762

申请日：2020-07-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Gang Zhao ,  Howard David ,  Xusheng Liu ,  Yongyao Li

IPC: G01R31/317 ,  G11C29/02 ,  G11C29/56

Abstract: A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.