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32 条记录 (耗时 0.03 秒)

    Method of monitoring high tilt angle of medium current implant
    1.
    发明授权
    Method of monitoring high tilt angle of medium current implant 失效
    监测中等电流植入物高倾角的方法

    公开(公告)号：US06924215B2

    公开(公告)日：2005-08-02

    申请号：US10157558

    申请日：2002-05-29

    申请人： Hung-Ta Huang ,  Hsueh-Li Sun ,  Juinn-Jie Chang ,  Stanley Huang ,  Jih-Churng Twu ,  Tom Tseng

    发明人： Hung-Ta Huang ,  Hsueh-Li Sun ,  Juinn-Jie Chang ,  Stanley Huang ,  Jih-Churng Twu ,  Tom Tseng

    IPC分类号： H01J37/304 ,  H01L21/66 ,  H01L21/336 ,  H01L21/265 ,  H01L21/331 ,  H01L21/36 ,  H01L21/425

    CPC分类号： H01L22/20 ,  H01J37/3045 ,  H01J2237/31701

    摘要： A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to the path of an ion beam; positioning a n-type wafer without screen oxide in the wafer holder; implanting boron species into a region of the wafer at 160 KeV and a dose level of 5.0×1013 atoms/cm2; periodically measuring the sheet resistivity of a implanted wafer and readjusting the wafer tilt angle when the sheet resistivity is greater than 30 ohms/square.

    摘要翻译： 一种监测和调整晶片相对于离子束的位置的方法，包括设置晶片保持器的位置，使得待保持在其中的晶片位于45度的倾斜角度和45度的扭转角度， 相对于离子束的路径; 将没有荧光体氧化物的n型晶片定位在晶片保持器中; 在160KeV下将硼物质注入晶片的区域，并且剂量水平为5.0×10 3原子/ cm 2; 周期性地测量植入晶片的片电阻率，并且当片电阻率大于30欧姆/平方时重新调整晶片倾斜角。

    Metrology for monitoring a rapid thermal annealing process
    2.
    发明授权
    Metrology for monitoring a rapid thermal annealing process 失效
    用于监测快速热退火过程的计量

    公开(公告)号：US06777251B2

    公开(公告)日：2004-08-17

    申请号：US10175702

    申请日：2002-06-20

    申请人： Ching Shan Lu ,  Fu-Su Lee ,  Wei-Ming You ,  Jih-Churng Twu ,  Yu-Chien Hsiao

    发明人： Ching Shan Lu ,  Fu-Su Lee ,  Wei-Ming You ,  Jih-Churng Twu ,  Yu-Chien Hsiao

    IPC分类号： H01L2166

    CPC分类号： H01L21/67253 ,  H01L21/67098 ,  H01L22/20

    摘要： A method including operating an ion implanted to implanting ions in a semiconductor wafer at a first ion dose level; performing a first thermal wave measurement to obtain the first thermal wave value; placing the semiconductor wafer in a rapid thermal annealing furnace and operating the furnace to rapidly heat the semiconductor wafer at a first rate for a first time period and so that the wafer is heated with intent of achieving a wafer temperature of 500° C.; performing a second thermal wave measurement to obtain a second thermal wave value; comparing the difference between the first thermal wave value and the second thermal wave value to a target range of 376.5-382.5 and rejecting the wafer as being outside of an acceptable specification if the difference is outside of the target range.

    摘要翻译： 一种方法，包括操作注入的离子以在第一离子剂量水平下在半导体晶片中注入离子; 执行第一热波测量以获得第一热波值; 将半导体晶片放置在快速热退火炉中并操作炉子以第一速率第一时间段快速加热半导体晶片，并且旨在实现晶片温度为500℃的晶片被加热; 执行第二热波测量以获得第二热波值; 将第一热波值和第二热波值之间的差值与376.5-382.5的目标范围进行比较，并且如果差异在目标范围之外，则拒绝晶片超出可接受规范。

    Ventilated platen/polishing pad assembly for chemcial mechanical polishing and method of using
    3.
    发明授权
    Ventilated platen/polishing pad assembly for chemcial mechanical polishing and method of using 失效
    用于化学机械抛光的通风压板/抛光垫组件及其使用方法

    公开(公告)号：US06722949B2

    公开(公告)日：2004-04-20

    申请号：US09813238

    申请日：2001-03-20

    申请人： Tien-Chen Hu ,  Jih-Churng Twu

    发明人： Tien-Chen Hu ,  Jih-Churng Twu

    IPC分类号： B24B100

    CPC分类号： B24B37/16 ,  B24B37/26 ,  B24D7/10

    摘要： A ventilated platen/polishing pad assembly for chemical mechanical polishing copper conductors on a semiconductor wafer is disclosed. The ventilated platen is constructed by a platen having a multiplicity of apertures through a thickness of the platen, and a polishing pad that has a multiplicity of apertures for fluid communication with the multiplicity of apertures in the platen such that a gas can flow through the ventilated platen and the ventilated polishing pad to mix with a polishing slurry solution dispensed on top of the polishing pad. When an oxidizing gas is mixed with the slurry solution, the mass transfer process during the chemical mechanical polishing can be improved and thus improving the polishing uniformity of the copper surface. The invention further discloses a method for chemical mechanical polishing copper conductors on a semiconductor wafer by dispensing a polishing slurry/oxidizing gas mixture onto a top surface of a polishing pad for engaging a wafer surface and thus improving the polishing uniformity and preventing corrosion or erosion of the fresh copper surface by the acidic or basic components contained in the slurry solution.

    摘要翻译： 公开了一种在半导体晶片上用于化学机械抛光铜导体的通风压板/抛光垫组件。 通风压板由具有穿过压板的厚度的多个孔的压板构成，抛光垫具有多个孔，用于与压板中的多个孔流体连通，使得气体可以流过通风的 压板和通风的抛光垫与分配在抛光垫顶部的抛光浆液混合。 当将氧化性气体与浆料溶液混合时，可以提高化学机械研磨过程中的传质过程，从而提高铜表面的研磨均匀性。 本发明还公开了一种通过将抛光浆料/氧化气体混合物分配到抛光垫的顶表面上用于接合晶片表面从而提高抛光均匀性并防止腐蚀或腐蚀的方法，用于化学机械抛光半导体晶片上的铜导体 新鲜的铜表面由浆液中所含的酸性或碱性成分溶液组成。

    Lightly nitridation surface for preparing thin-gate oxides
    5.
    发明授权
    Lightly nitridation surface for preparing thin-gate oxides 有权
    用于制备薄栅氧化物的轻微氮化表面

    公开(公告)号：US06380056B1

    公开(公告)日：2002-04-30

    申请号：US09177190

    申请日：1998-10-23

    申请人： Shau-Lin Shue ,  Jih-Churng Twu

    发明人： Shau-Lin Shue ,  Jih-Churng Twu

    IPC分类号： H01L213105

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/518

    摘要： A method for forming a dielectric layer upon a silicon layer. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon layer. There is then formed through use of a first thermal annealing method employing a nitrogen containing annealing atmosphere in absence of an oxidizing material or a reducing material silicon nitride containing layer upon a partially consumed silicon layer derived from the silicon layer. There is then oxidized through use of a second thermal annealing method employing an oxidizing material containing atmosphere the silicon nitride containing layer to form an oxidized silicon nitride containing layer upon a further consumed silicon layer derived from the partially consumed silicon layer. The method is particularly useful in forming a gate dielectric layer with enhanced hot carrier resistance properties and enhanced dopant diffusion barrier properties within a field effect transistor (FET).

    摘要翻译： 一种在硅层上形成电介质层的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成硅层。 然后通过在不存在氧化材料的情况下使用含氮退火气氛的第一热退火方法或者衍生自硅层的部分消耗的硅层上的还原材料氮化硅含有层形成第一热退火方法。 然后通过使用含有含氮化硅的层的氧化材料的第二热退火方法，在从部分消耗的硅层衍生的进一步消耗的硅层上形成氧化的含氮化硅的层而进行氧化。 该方法特别适用于在场效应晶体管（FET）中形成具有增强的热载流子电阻特性和增强的掺杂剂扩散阻挡特性的栅极介电层。

    Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity
    6.
    发明授权
    Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity 有权
    后化学机械抛光（CMP）平面化基板清洗方法采用增强的基板亲水性

    公开(公告)号：US06376377B1

    公开(公告)日：2002-04-23

    申请号：US09541487

    申请日：2000-04-03

    申请人： Weng Chang ,  Ying-Ho Chen ,  Jih-Churng Twu ,  Syun-Ming Jang

    发明人： Weng Chang ,  Ying-Ho Chen ,  Jih-Churng Twu ,  Syun-Ming Jang

    IPC分类号： H01L21302

    CPC分类号： H01L21/76826 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76888

    摘要： Within a method for removing from over a substrate a chemical mechanical polish (CMP) residue layer there is first provided a substrate. There is then formed over the substrate: (1) a chemical mechanical polish (CMP) substrate layer having an aperture formed therein; (2) a chemical mechanical polish (CMP) planarized patterned layer formed within the aperture within the chemical mechanical polish (CMP) substrate layer; and (3) a chemical mechanical polish (CMP) residue layer formed upon at least one of the chemical mechanical polish substrate layer and the chemical mechanical polish (CMP) planarized patterned layer, where at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer has a first aqueous contact angle. There is then treated the at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer having the first aqueous contact angle to provide at least one of a hydrophilic chemical mechanical polish (CMP) substrate layer and a hydrophilic chemical mechanical polish (CMP) planarized patterned layer having a second aqueous contact angle less than the first aqueous contact angle. Finally, there is then removed the chemical mechanical polish (CMP) residue layer from the at least one of the hydrophilic chemical mechanical polish (CMP) substrate layer and the hydrophilic chemical mechanical polish (CMP) planarized patterned layer with an aqueous cleaner composition.

    摘要翻译： 在用于从衬底上除去化学机械抛光（CMP）残留层的方法中，首先提供衬底。 然后在衬底上形成：（1）其中形成有孔的化学机械抛光（CMP）衬底层; （2）化学机械抛光（CMP）平面化图案层，其形成在化学机械抛光（CMP）衬底层内的孔内; 化学机械抛光（CMP）残留层形成在至少一个化学机械抛光衬底层和化学机械抛光（CMP）平面化图案层上，其中化学机械抛光（CMP）衬底 层和化学机械抛光（CMP）平面化图案层具有第一水接触角。 然后，处理具有第一水接触角的化学机械抛光（CMP）衬底层和化学机械抛光（CMP）平坦化图案化层中的至少一个以提供亲水化学机械抛光（CMP）衬底中的至少一个 层和亲水化学机械抛光（CMP）平面化图案层，其具有小于第一水接触角的第二水接触角。 最后，用水性清洁剂组合物从亲水化学机械抛光（CMP）衬底层和亲水化学机械抛光（CMP）平坦化图案化层中的至少一个去除化学机械抛光（CMP）残留层。

    Wet oxidation method for forming silicon oxide dielectric layer
    7.
    发明授权
    Wet oxidation method for forming silicon oxide dielectric layer 有权
    用于形成氧化硅介电层的湿式氧化法

    公开(公告)号：US06211098B1

    公开(公告)日：2001-04-03

    申请号：US09252337

    申请日：1999-02-18

    申请人： Jih-Churng Twu ,  Syun-Ming Jang ,  Chen-Hua Yu

    发明人： Jih-Churng Twu ,  Syun-Ming Jang ,  Chen-Hua Yu

    IPC分类号： H01L2126

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/517 ,  H01L29/518

    摘要： A method for forming a silicon oxide gate oxide dielectric layer upon a silicon semiconductor substrate employed within a microelectronics fabrication. There is provided a silicon semiconductor substrate. There is then formed upon the silicon semiconductor substrate, empolying thermal annealing of the silicon semiconductor substrate at an elevated temperature in a gas mixture of oxygen, hydrogen and a diluent gas, a silicon oxide gate oxide dielectric layer with enhanced dielectric properties and more precise control of the silicon oxide dielectric layer thickness.

    摘要翻译： 一种在微电子学制造中使用的硅半导体衬底上形成氧化硅栅极氧化物电介质层的方法。 提供硅半导体衬底。 然后形成在硅半导体衬底上，在氧气，氢气和稀释气体的气体混合物中，在升高的温度下对硅半导体衬底进行热退火，具有增强介电特性和更精确控制的氧化硅栅氧化物介电层 的氧化硅介电层厚度。

    Multilayer interface in copper CMP for low K dielectric
    8.
    发明授权
    Multilayer interface in copper CMP for low K dielectric 有权
    用于低K电介质的铜CMP中的多层界面

    公开(公告)号：US06753249B1

    公开(公告)日：2004-06-22

    申请号：US09759908

    申请日：2001-01-16

    申请人： Ying-Ho Chen ,  Jih-Churng Twu ,  Weng Chang

    发明人： Ying-Ho Chen ,  Jih-Churng Twu ,  Weng Chang

    IPC分类号： H01L214763

    CPC分类号： H01L21/7684

    摘要： An improved and new process, used for the elimination of copper line damage, copper defects, non-uniformity improvement, with low dishing and erosion, in damacene processing, is disclosed. This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface.

    摘要翻译： 公开了一种改进的新工艺，用于消除铜线损伤，铜缺陷，不均匀性改进，具有较低的凹陷和侵蚀。 本发明涉及一种用于半导体集成电路器件的制造方法，更具体地说，涉及通过在低温下沉积由机械硬膜和软膜组成的多层界面材料来消除镶嵌加工中的铜线损伤 介电常数，层间金属电介质（IMD）和随后的化学机械抛光（CMP）回退多余的材料以使表面平坦化。

    Method for high temperature oxidations to prevent oxide edge peeling
    9.
    发明授权
    Method for high temperature oxidations to prevent oxide edge peeling 有权
    高温氧化防止氧化皮边缘剥落的方法

    公开(公告)号：US06642128B1

    公开(公告)日：2003-11-04

    申请号：US10140396

    申请日：2002-05-06

    申请人： Ching-Shan Lu ,  Kuo-Bin Huang ,  Jih-Churng Twu

    发明人： Ching-Shan Lu ,  Kuo-Bin Huang ,  Jih-Churng Twu

    IPC分类号： H01L21322

    CPC分类号： H01L21/76224

    摘要： A method for preventing oxide layer peeling in a high temperature annealing process including providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including an oxide layer of at least one semiconductor wafer is adjacent to a backside surface of another semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process; and, carrying out the high temperature annealing process.

    摘要翻译： 一种用于防止在高温退火过程中氧化层剥离的方法，包括提供多个间隔堆叠的半导体晶片，用于执行包括环境氮气的高温退火工艺，所述多个间隔堆叠的半导体晶片被堆叠，使得处理表面包括 在进行高温退火处理之前，至少一个半导体晶片的氧化物层与另一半导体晶片的背面相邻，所述背面具有形成在其上的氮化硅层; 并进行高温退火处理。