公开(公告)号：US06600338B1

公开(公告)日：2003-07-29

申请号：US09849755

申请日：2001-05-04

Applicant: Huy Nguyen ,  Roxanne Vu ,  Benedict Lau ,  Jade Kizer

Inventor： Huy Nguyen ,  Roxanne Vu ,  Benedict Lau ,  Jade Kizer

IPC: H03K190175

CPC classification number: H03K19/018528

Abstract: A circuit and method for level-shifting an input signal are disclosed that provide for level-shifting of a the input signal where an external voltage level is greater than an internal voltage of the signal. In the present invention, the input signal is compared to a reference signal to produce a differential current signal reflecting the logic level of the input signal. The differential current signal is reflected through a pair of current mirrors operating from the external voltage level to drive a pair of resistive loads. Each of the resistive loads is coupled in series with a current sink between the internal supply voltage and a ground voltage. As a result, the input signal may be received and level-shifted with gain even when the internal supply voltage is less than twice a transistor threshold voltage without introducing significant distortion to the received signal.

Abstract translation: 公开了用于电平移位输入信号的电路和方法，其提供输入信号的电平移位，其中外部电压电平大于信号的内部电压。 在本发明中，将输入信号与参考信号进行比较，以产生反映输入信号的逻辑电平的差分电流信号。 差分电流信号通过从外部电压电平工作的一对电流镜反射，以驱动一对电阻负载。 每个电阻负载与内部电源电压和接地电压之间的电流吸收器串联耦合。 结果，即使当内部电源电压小于晶体管阈值电压的两倍时，也可以接收输入信号并进行电平移位，而不会对接收到的信号引入显着的失真。

公开(公告)号：US06798243B1

公开(公告)日：2004-09-28

申请号：US10629167

申请日：2003-07-28

Applicant: Huy Nguyen ,  Roxanne Vu ,  Benedict Lau ,  Jade Kizer

Inventor： Huy Nguyen ,  Roxanne Vu ,  Benedict Lau ,  Jade Kizer

IPC: H03K190175

CPC classification number: H03K19/018528

Abstract: A circuit and method for level-shifting an input signal are disclosed that provide for level-shifting of a the input signal where an external voltage level is greater than an internal voltage of the signal. In the present invention, the input signal is compared to a reference signal to produce a differential current signal reflecting the logic level of the input signal. The differential current signal is reflected through a pair of current mirrors operating from the external voltage level to drive a pair of resistive loads. Each of the resistive loads is coupled in series with a current sink between the internal supply voltage and a ground voltage. As a result, the input signal may be received and level-shifted with gain even when the internal supply voltage is less than twice a transistor threshold voltage without introducing significant distortion to the received signal.

Abstract translation: 公开了用于电平移位输入信号的电路和方法，其提供输入信号的电平移位，其中外部电压电平大于信号的内部电压。 在本发明中，将输入信号与参考信号进行比较，以产生反映输入信号的逻辑电平的差分电流信号。 差分电流信号通过从外部电压电平工作的一对电流镜反射，以驱动一对电阻负载。 每个电阻负载与内部电源电压和接地电压之间的电流吸收器串联耦合。 结果，即使当内部电源电压小于晶体管阈值电压的两倍时，也可以接收输入信号并进行电平移位，而不会对接收到的信号引入显着的失真。

公开(公告)号：US20050001662A1

公开(公告)日：2005-01-06

申请号：US10852650

申请日：2004-05-24

Applicant: Jade Kizer ,  Benedict Lau ,  Roxanne Vu ,  Craig Hampel

Inventor： Jade Kizer ,  Benedict Lau ,  Roxanne Vu ,  Craig Hampel

IPC: G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H03L7/06

CPC classification number: H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0814

Abstract: An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Abstract translation: 一种具有选择电路，加法电路和相位混频器的集成电路装置。 选择电路选择多个偏移值中的一个作为选择的偏移。 求和电路将所选择的偏移与相位计数值相加，相位计数值指示参考时钟信号和第一多个时钟信号之间的相位差。 相位混频器根据所选择的偏移和相位计数值的和来组合第一多个时钟信号以产生输出时钟信号。

公开(公告)号：US20050030071A1

公开(公告)日：2005-02-10

申请号：US10633831

申请日：2003-08-04

Applicant: Huy Nguyen ,  Benedict Lau ,  Leung Yu ,  Jade Kizer

Inventor： Huy Nguyen ,  Benedict Lau ,  Leung Yu ,  Jade Kizer

IPC: G06F1/10 ,  H03L7/00 ,  H03L7/06

CPC classification number: G06F1/10 ,  G06F1/12 ,  H03L7/00

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract translation: 用于同步计时器件的电路和方法，例如寄存器。 由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。 通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

公开(公告)号：US20050046454A1

公开(公告)日：2005-03-03

申请号：US10963698

申请日：2004-10-13

Applicant: Huy Nguyen ,  Benedict Lau ,  Leung Yu ,  Jade Kizer

Inventor： Huy Nguyen ,  Benedict Lau ,  Leung Yu ,  Jade Kizer

IPC: G06F1/10 ,  H03L7/00 ,  H03L7/06

CPC classification number: G06F1/10 ,  G06F1/12 ,  H03L7/00

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract translation: 用于同步计时器件的电路和方法，例如寄存器。 由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。 通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

公开(公告)号：US20070124636A1

公开(公告)日：2007-05-31

申请号：US11620309

申请日：2007-01-05

Applicant: Huy Nguyen ,  Benedict Lau ,  Leung Yu ,  Jade Kizer

Inventor： Huy Nguyen ,  Benedict Lau ,  Leung Yu ,  Jade Kizer

IPC: G01R31/28

CPC classification number: G06F1/10 ,  G06F1/12 ,  H03L7/00

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract translation: 用于同步计时器件的电路和方法，例如寄存器。 由于不同的传播延迟，寄存器由具有相同频率但潜在不同相位的各个组件时钟信号计时。 通过对寄存器中的分量时钟信号的相位进行评估，使寄存器接收到的单独的分量时钟信号变为相位，并且将序列中的每个寄存器的分量时钟信号与先前寄存器的分量时钟信号同步。

公开(公告)号：US07095265B2

公开(公告)日：2006-08-22

申请号：US11101958

申请日：2005-04-08

Applicant: Huy Nguyen ,  Roxanne Vu ,  Benedict Lau

Inventor： Huy Nguyen ,  Roxanne Vu ,  Benedict Lau

IPC: G06F1/04

CPC classification number: H03K5/133 ,  G06F1/10 ,  H03K2005/00039 ,  H03K2005/00078 ,  H03K2005/00143

Abstract: Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the clock buffers in response to process, voltage, and temperature variations, and consequently maintains a relatively constant signal-propagation delay through the network. In one embodiment, each clock buffer includes skew-offset circuitry that adds to or subtracts from the PVT compensated delay values provided by the PVT control circuit to simplify clock skew minimization.

Abstract translation: 描述了用于分配低偏移，可预测的定时时钟信号的方法和系统。 时钟分配网络包括多个可动态调整的时钟缓冲器。 连接到每个时钟缓冲器的控制电路响应于过程，电压和温度变化来控制通过时钟缓冲器的延迟，并且因此通过网络维持相对恒定的信号传播延迟。 在一个实施例中，每个时钟缓冲器包括倾斜偏移电路，其增加或减去由PVT控制电路提供的PVT补偿延迟值，以简化时钟偏差最小化。

公开(公告)号：US20050058233A1

公开(公告)日：2005-03-17

申请号：US10661225

申请日：2003-09-12

Applicant: Huy Nguyen ,  Roxanne Vu ,  Leung Yu ,  Benedict Lau

Inventor： Huy Nguyen ,  Roxanne Vu ,  Leung Yu ,  Benedict Lau

IPC: G11C7/10 ,  G11C7/22 ,  H04L7/00

CPC classification number: G11C7/1093 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

Abstract: A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for different data signal types and different slave devices. In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle. The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received. In a receiver system utilizing a clock tree, individual branches of the clock tree are configured to have respective duty cycles skewed to match the duty cycle of a data signal received from a specific transmitting device.

Abstract translation: 一种用于配置接收机的系统和方法，使得接收机时钟的占空比与接收到的数据信号的占空比精确匹配。 该自适应系统和方法校准接收机的占空比，以优化不同数据信号类型和不同从设备的接收机定时裕度。 在一个实施例中，占空比校正电路将接收器时钟与预定的占空比相匹配。 然后，接收机时钟被配置为具有基于接收的特定数据信号从预定占空比偏移的占空比。 在利用时钟树的接收机系统中，时钟树的各个分支被配置成使各自的占空比歪斜以匹配从特定发送设备接收的数据信号的占空比。

公开(公告)号：US06806728B2

公开(公告)日：2004-10-19

申请号：US09930694

申请日：2001-08-15

Applicant: Huy Nguyen ,  Roxanne Vu ,  Benedict Lau

Inventor： Huy Nguyen ,  Roxanne Vu ,  Benedict Lau

IPC: H03K1716

CPC classification number: G06F13/4086

Abstract: A circuit and method for interfacing to a bus via an on-die termination pad are shown. The present invention derives an output low reference voltage from an external terminating voltage and an external reference voltage corresponding to the middle of a logic voltage range. A feedback loop is used to compare a voltage at the pad to the output low reference voltage. An on-die termination current sourced to the pad is adjusted accordingly. This allows the present invention to adapt to a variety of external termination voltages. Further, the output low reference voltage is utilized to generate a reference current sourced to an output amplifier, which causes the output swing of the amplifier to track along with the external terminating voltage and the external reference voltage. In another aspect of the present invention, an alternating pattern of logic high and logic low voltage values is transmitted at the pad and received. The received data pattern is compared to the transmitted data pattern to adjust the on-die termination current and the reference current.

Abstract translation: 示出了通过片上终端焊盘与总线接口的电路和方法。 本发明从外部终端电压和对应于逻辑电压范围中间的外部基准电压得出输出低参考电压。 反馈回路用于将焊盘上的电压与输出低参考电压进行比较。 相应地调整源于焊盘的片上端接电流。 这允许本发明适应各种外部终端电压。 此外，输出低参考电压用于产生源自输出放大器的参考电流，这使得放大器的输出摆幅与外部终端电压和外部参考电压一起跟踪。 在本发明的另一方面，逻辑高电平和逻辑低电压值的交替模式在焊盘处被传输并被接收。 将接收到的数据模式与发送的数据模式进行比较，以调整片上终端电流和参考电流。

公开(公告)号：US20050237117A1

公开(公告)日：2005-10-27

申请号：US10828667

申请日：2004-04-21

Applicant: Roxanne Vu ,  Huy Nguyen ,  Benedict Lau

Inventor： Roxanne Vu ,  Huy Nguyen ,  Benedict Lau

IPC: H03L7/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/18 ,  H04L7/033

CPC classification number: H03L7/0898 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1075 ,  H03L7/18 ,  H04L7/033

Abstract: A PLL circuit and method provides an adjustable operating frequency range by using at least two VCOs. In an embodiment of the present invention, circuit components of a PLL are adjusted in order to obtain a selected frequency range. In particular, a gain of a charge pump and resistance of a filter is adjusted responsive to a control signal. In alternate embodiments of the present invention, a voltage regulator, including an operational amplifier, is coupled to the output of the filter and the respective inputs of two VCOs. An output multiplexer then selects a VCO output responsive to the control signal. In another embodiment of the present invention, a multiplexer is coupled to the output of the voltage regulator to select which VCO receives a buffered voltage. In another embodiment of the present invention, respective operational amplifiers that may be enabled or disabled responsive to the control signal are coupled to a filter output and respective VCO inputs in order to provide an adjustable frequency range.

Abstract translation: PLL电路和方法通过使用至少两个VCO提供可调节的工作频率范围。 在本发明的一个实施例中，调整PLL的电路部件以获得选定的频率范围。 特别地，响应于控制信号调整电荷泵的增益和滤波器的电阻。 在本发明的替代实施例中，包括运算放大器的电压调节器耦合到滤波器的输出端和两个VCO的相应输入端。 然后，输出多路复用器响应于控制信号选择VCO输出。 在本发明的另一个实施例中，多路复用器耦合到电压调节器的输出以选择哪个VCO接收缓冲电压。 在本发明的另一个实施例中，可以响应于控制信号使能或禁用的各个运算放大器被耦合到滤波器输出和相应的VCO输入，以便提供可调节的频率范围。