公开(公告)号：US07494866B2

公开(公告)日：2009-02-24

申请号：US11403901

申请日：2006-04-14

申请人： Hwa-Young Ko ,  Kyung-Rae Byun ,  Hyoung-Seub Rhie ,  Hee-Seok Kim ,  Jin-Hwan Ham ,  Suk-Ho Joo

发明人： Hwa-Young Ko ,  Kyung-Rae Byun ,  Hyoung-Seub Rhie ,  Hee-Seok Kim ,  Jin-Hwan Ham ,  Suk-Ho Joo

IPC分类号： H01L21/8242

CPC分类号： H01L23/485 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/65 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.

摘要翻译： 公开了半导体器件和相关的制造方法。 半导体器件包括半导体衬底，包括形成在半导体衬底上的接触区域和栅极结构的导电结构，形成在栅极结构上的保护层，形成在保护层上的绝缘层，以及直接接触触点的多个触点 区域和半导体衬底通过绝缘层，其中触点彼此具有实质上不同的高度。

公开(公告)号：US20060237851A1

公开(公告)日：2006-10-26

申请号：US11403901

申请日：2006-04-14

申请人： Hwa-Young Ko ,  Kyung-Rae Byun ,  Hyoung-Seub Rhie ,  Hee-Seok Kim ,  Jin-Hwan Ham ,  Suk-Ho Joo

发明人： Hwa-Young Ko ,  Kyung-Rae Byun ,  Hyoung-Seub Rhie ,  Hee-Seok Kim ,  Jin-Hwan Ham ,  Suk-Ho Joo

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/65 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.

公开(公告)号：US20060273366A1

公开(公告)日：2006-12-07

申请号：US11447545

申请日：2006-06-06

申请人： Hwa-Young Ko ,  Suk-Ho Joo ,  Byoung-Jae Bae ,  Hee-Seok Kim ,  Kyung-Rae Byun ,  Jin-Hwan Ham

发明人： Hwa-Young Ko ,  Suk-Ho Joo ,  Byoung-Jae Bae ,  Hee-Seok Kim ,  Kyung-Rae Byun ,  Jin-Hwan Ham

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  H01L21/32139 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： In a method of manufacturing a ferroelectric capacitor, a lower electrode layer is formed on a substrate. The lower electrode layer includes at least one lower electrode film. A ferroelectric layer is formed on the lower electrode layer, and then an upper electrode layer is formed on the ferroelectric layer. A hard mask structure is formed on the upper electrode layer. The hard mask structure includes a first hard mask and a second hard mask. An upper electrode, a ferroelectric layer pattern and a lower electrode are formed by partially etching the upper electrode layer, the ferroelectric layer and the lower electrode layer using the hard mask structure. The hard mask structure may prevent damage to the ferroelectric layer and may enlarge an effective area of the ferroelectric capacitor so that the ferroelectric capacitor may have enhanced electrical and ferroelectric characteristics.

摘要翻译： 在制造铁电电容器的方法中，在基板上形成下电极层。 下电极层包括至少一个下电极膜。 在下电极层上形成铁电体层，在铁电层上形成上电极层。 在上电极层上形成硬掩模结构。 硬掩模结构包括第一硬掩模和第二硬掩模。 通过使用硬掩模结构部分蚀刻上电极层，铁电层和下电极层，形成上电极，铁电层图案和下电极。 硬掩模结构可以防止对铁电层的损坏，并且可以增加铁电电容器的有效面积，使得铁电电容器可以具有增强的电和铁电特性。

公开(公告)号：US20050148201A1

公开(公告)日：2005-07-07

申请号：US10981731

申请日：2004-11-05

申请人： Jae-Young Ahn ,  Jin-Gyun Kim ,  Hee-Seok Kim ,  Jin-Tae No ,  Sang-Ryol Yang ,  Sung-Hae Lee ,  Hong-Suk Kim ,  Ju-Wan Lim ,  Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sug Kang

发明人： Jae-Young Ahn ,  Jin-Gyun Kim ,  Hee-Seok Kim ,  Jin-Tae No ,  Sang-Ryol Yang ,  Sung-Hae Lee ,  Hong-Suk Kim ,  Ju-Wan Lim ,  Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sug Kang

IPC分类号： C23C16/30 ,  C23C16/44 ,  C23C16/455 ,  H01L21/318 ,  H01L21/321 ,  H01L21/44

CPC分类号： H01L21/0228 ,  C23C16/30 ,  C23C16/45531 ,  H01L21/02274 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/3211

摘要： A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

摘要翻译： 一种用于使用ALD工艺形成用于半导体器件的低k电介质层的方法，包括（a）在半导体衬底上形成预定的互连图案，（b）向其中具有衬底的室提供第一和第二反应性材料， 从而将第一和第二反应性材料吸附在衬底的表面上，（c）向腔室供应第一气体以清除保留未反应的第一和第二反应性材料，（d）向室提供第三反应性材料，从而 引起所述第一和第二材料和所述第三反应性材料之间的反应以形成单层，（e）向所述室供应第二气体以吹扫在所述室中保留未反应的第三反应性材料和副产物; 和（f）重复（b）至（e）预定次数以在基板上形成具有预定厚度的SiBN三元层。

公开(公告)号：US07759192B2

公开(公告)日：2010-07-20

申请号：US11258619

申请日：2005-10-24

申请人： Jae-Young Ahn ,  Jin-Tae Noh ,  Hee-Seok Kim ,  Jin-Gyun Kim ,  Ju-Wan Lim ,  Sang-Ryol Yang ,  Hong-Suk Kim ,  Sung-Hae Lee

发明人： Jae-Young Ahn ,  Jin-Tae Noh ,  Hee-Seok Kim ,  Jin-Gyun Kim ,  Ju-Wan Lim ,  Sang-Ryol Yang ,  Hong-Suk Kim ,  Sung-Hae Lee

IPC分类号： H01L21/8242

CPC分类号： H01L21/02178 ,  H01L21/02181 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/91

摘要： A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and a doped polysilicon layer epitaxially deposited on the doped poly-Si1-xGex layer and the contact plug makes a contact with the doped polysilicon layer.

摘要翻译： 半导体器件包括具有底部电极的电容器，形成在底部电极上的电介质层，形成在电介质层上的顶部电极和具有与顶部电极连接的金属的接触插塞，其中顶部电极包括 掺杂多晶Si1-xGex层和外延沉积在掺杂多晶Si1-xGex层上的掺杂多晶硅层和接触插塞与掺杂多晶硅层接触。

公开(公告)号：US20060097299A1

公开(公告)日：2006-05-11

申请号：US11258619

申请日：2005-10-24

申请人： Jae-Young Ahn ,  Jin-Tae Noh ,  Hee-Seok Kim ,  Jin-Gyun Kim ,  Ju-Wan Lim ,  Sang-Ryol Yang ,  Hong-Suk Kim ,  Sung-Hae Lee

发明人： Jae-Young Ahn ,  Jin-Tae Noh ,  Hee-Seok Kim ,  Jin-Gyun Kim ,  Ju-Wan Lim ,  Sang-Ryol Yang ,  Hong-Suk Kim ,  Sung-Hae Lee

IPC分类号： H01L29/94

CPC分类号： H01L21/02178 ,  H01L21/02181 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/91

摘要： A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and a doped polysilicon layer epitaxially deposited on the doped poly-Si1-xGex layer and the contact plug makes a contact with the doped polysilicon layer.

摘要翻译： 半导体器件包括具有底部电极的电容器，形成在底部电极上的电介质层，形成在电介质层上的顶部电极和具有与顶部电极连接的金属的接触插塞，其中顶部电极包括 掺杂的多晶硅1-x Ge层和外延沉积在掺杂的多晶Si-x Ge层上的掺杂多晶硅层 并且接触插塞与掺杂多晶硅层接触。

公开(公告)号：US06962876B2

公开(公告)日：2005-11-08

申请号：US10981731

申请日：2004-11-05

申请人： Jae-Young Ahn ,  Jin-Gyun Kim ,  Hee-Seok Kim ,  Jin-Tae No ,  Sang-Ryol Yang ,  Sung-Hae Lee ,  Hong-Suk Kim ,  Ju-Wan Lim ,  Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sug Kang

发明人： Jae-Young Ahn ,  Jin-Gyun Kim ,  Hee-Seok Kim ,  Jin-Tae No ,  Sang-Ryol Yang ,  Sung-Hae Lee ,  Hong-Suk Kim ,  Ju-Wan Lim ,  Young-Seok Kim ,  Yong-Woo Hyung ,  Man-Sug Kang

IPC分类号： C23C16/30 ,  C23C16/44 ,  C23C16/455 ,  H01L21/318 ,  H01L21/321 ,  H01L21/44 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0228 ,  C23C16/30 ,  C23C16/45531 ,  H01L21/02274 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/3211

摘要： A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

公开(公告)号：US08469637B2

公开(公告)日：2013-06-25

申请号：US13214628

申请日：2011-08-22

申请人： Chang Hee Choi ,  Chang Gyu Park ,  Hee-Seok Kim

发明人： Chang Hee Choi ,  Chang Gyu Park ,  Hee-Seok Kim

IPC分类号： B23C5/10 ,  B23C5/20

CPC分类号： B23C5/1036 ,  B23C5/109 ,  B23C2200/361 ,  Y10T407/14 ,  Y10T407/2274 ,  Y10T407/23

摘要： A cutting insert has an upper face and a lower face; a front side face portion and a back side face portion, the front and back side face portions connecting the upper face and the lower face; and a through-hole passing through the upper face and the lower face. A cutting edge is formed in the front side face portion, and the back side face portion is provided with a first inclined face and a second inclined face which are inclined forwardly at different angles, respectively, with respect to a plane normal to a rotational axis. The first inclined face is longer than the second inclined face so that the back side face portion has a non-symmetrical convex “V” shape.

摘要翻译： 切削刀片具有上表面和下表面; 前侧面部分和后侧面部分，前后面部分连接上表面和下表面; 以及穿过上表面和下表面的通孔。 在前侧面部形成有切削刃，后侧面部设有分别相对于与旋转轴垂直的平面以不同的角度向前倾斜的第一倾斜面和第二倾斜面 。 第一倾斜面比第二倾斜面长，使得背面面部具有非对称的凸形“V”形状。

公开(公告)号：US20110299945A1

公开(公告)日：2011-12-08

申请号：US13214628

申请日：2011-08-22

申请人： Chang Hee Choi ,  Chang Gyu Park ,  Hee-Seok Kim

发明人： Chang Hee Choi ,  Chang Gyu Park ,  Hee-Seok Kim

IPC分类号： B23C5/22 ,  B23B27/16 ,  B23B27/10 ,  B23C5/28

CPC分类号： B23C5/1036 ,  B23C5/109 ,  B23C2200/361 ,  Y10T407/14 ,  Y10T407/2274 ,  Y10T407/23

摘要： A cutting insert has an upper face and a lower face; a front side face portion and a back side face portion, the front and back side face portions connecting the upper face and the lower face; and a through-hole passing through the upper face and the lower face. A cutting edge is formed in the front side face portion, and the back side face portion is provided with a first inclined face and a second inclined face which are inclined forwardly at different angles, respectively, with respect to a plane normal to a rotational axis. The first inclined face is longer than the second inclined face so that the back side face portion has a non-symmetrical convex “V” shape.

摘要翻译： 切削刀片具有上表面和下表面; 前侧面部分和后侧面部分，前后面部分连接上表面和下表面; 以及穿过上表面和下表面的通孔。 在前侧面部形成有切削刃，后侧面部设有分别相对于与旋转轴垂直的平面以不同的角度向前倾斜的第一倾斜面和第二倾斜面 。 第一倾斜面比第二倾斜面长，使得背面面部具有非对称的凸形“V”形状。

公开(公告)号：US07488694B2

公开(公告)日：2009-02-10

申请号：US11031611

申请日：2005-01-07

申请人： Jin-Gyun Kim ,  Jae-Young Ahn ,  Hee-Seok Kim ,  Ju-Wan Lim

发明人： Jin-Gyun Kim ,  Jae-Young Ahn ,  Hee-Seok Kim ,  Ju-Wan Lim

IPC分类号： H01L21/44

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/45553 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3185

摘要： The present invention provides nitrogenous compositions for forming a silicon nitride layer, wherein the nitrogenous composition comprises a hydrazine compound, an amine compound or a mixture thereof. The present invention further provides source compositions for forming a silicon nitride layer, wherein the source composition comprises a nitrogenous composition comprising a hydrazine compound, an amine compound or a mixture thereof, and a silicon source comprising hexachlorodisilane. Methods for forming silicon nitride layers are further provided. The silicon nitride layers provided herein may be formed on a substrate at a low temperature and may further exhibit improved breakdown voltage and an enhanced etch resistance.

摘要翻译： 本发明提供了用于形成氮化硅层的含氮组合物，其中含氮组合物包含肼化合物，胺化合物或其混合物。 本发明还提供了用于形成氮化硅层的源组合物，其中源组合物包含含氮化合物，胺化合物或其混合物的含氮组合物和包含六氯二硅烷的硅源。 还提供了形成氮化硅层的方法。 本文提供的氮化硅层可以在低温下形成在衬底上，并且可以进一步显示出改进的击穿电压和增强的耐蚀刻性。