公开(公告)号：US20100167212A1

公开(公告)日：2010-07-01

申请号：US12654742

申请日：2009-12-30

申请人： Hyeon-Mo Cho ,  Sang-Kyun Kim ,  Mi-Young Kim ,  Sang-Ran Koh ,  Hui-Chang Yun ,  Yong-Jin Chung ,  Jong-Seob Kim ,  In-Sun Jung

发明人： Hyeon-Mo Cho ,  Sang-Kyun Kim ,  Mi-Young Kim ,  Sang-Ran Koh ,  Hui-Chang Yun ,  Yong-Jin Chung ,  Jong-Seob Kim ,  In-Sun Jung

IPC分类号： G03F7/20 ,  C08L61/00 ,  C08L83/00 ,  C08K5/3432 ,  C08G77/00

CPC分类号： G03F7/11 ,  C08K5/54 ,  G03F7/0752

摘要： A resist underlayer composition and a method of manufacturing a semiconductor integrated circuit device, the resist underlayer composition including a solvent and an organosilane-based polymer, the organosilane-based polymer being a polymerization product of at least one first compound represented Chemical Formulae 1 to 3 and at least one second compound represented by Chemical Formulae 4 and 5.

摘要翻译： 抗蚀剂下层组合物和半导体集成电路器件的制造方法，所述抗蚀剂底层组合物包含溶剂和有机硅烷系聚合物，所述有机硅烷类聚合物为至少一种化学式1〜3的第一化合物的聚合产物 和由化学式4和5表示的至少一种第二化合物。

公开(公告)号：US09140986B2

公开(公告)日：2015-09-22

申请号：US13539760

申请日：2012-07-02

申请人： Mi-Young Kim ,  Sang-Kyun Kim ,  Hyeon-Mo Cho ,  Sang-Ran Koh ,  Hui-Chan Yun ,  Yong-Jin Chung ,  Jong-Seob Kim

发明人： Mi-Young Kim ,  Sang-Kyun Kim ,  Hyeon-Mo Cho ,  Sang-Ran Koh ,  Hui-Chan Yun ,  Yong-Jin Chung ,  Jong-Seob Kim

IPC分类号： C08G77/08 ,  G03F7/075 ,  G03F7/11 ,  H01L21/02 ,  H01L21/033 ,  C08L83/04 ,  C08G77/16 ,  C08G77/18 ,  C08L83/06

CPC分类号： G03F7/0752 ,  C08G77/16 ,  C08G77/18 ,  C08L83/04 ,  C08L83/06 ,  G03F7/11 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/0332

摘要： A resist underlayer composition includes a solvent and an organosilane condensation polymerization product, the organosilane condensation polymerization product including about 40 to about 80 mol % of a structural unit represented by the following Chemical Formula 1,

摘要翻译： 抗蚀剂底层组合物包括溶剂和有机硅烷缩聚产物，所述有机硅烷缩聚产物包含约40至约80mol％的由以下化学式1表示的结构单元，

公开(公告)号：US08357576B2

公开(公告)日：2013-01-22

申请号：US13007096

申请日：2011-01-14

申请人： Chong-Kwang Chang ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

发明人： Chong-Kwang Chang ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

摘要翻译： 一种制造半导体器件的方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅极图案，使得所述栅极图案包括栅极电介质层和牺牲栅电极; 在半导体衬底和栅极图案上形成蚀刻停止层和电介质层; 去除介电层的部分以暴露蚀刻停止层; 在所述蚀刻停止层上执行蚀刻工艺以暴露所述牺牲栅电极; 去除所述牺牲栅电极以形成沟槽; 在包括沟槽的半导体衬底上形成金属层; 去除所述金属层的部分以暴露所述介电层; 以及对所述金属层执行到预定目标的回蚀处理。

公开(公告)号：US20110195550A1

公开(公告)日：2011-08-11

申请号：US13007096

申请日：2011-01-14

申请人： Chong-Kwang CHANG ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

发明人： Chong-Kwang CHANG ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

摘要翻译： 一种制造半导体器件的方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅极图案，使得所述栅极图案包括栅极电介质层和牺牲栅电极; 在半导体衬底和栅极图案上形成蚀刻停止层和电介质层; 去除介电层的部分以暴露蚀刻停止层; 在所述蚀刻停止层上执行蚀刻工艺以暴露所述牺牲栅电极; 去除所述牺牲栅电极以形成沟槽; 在包括沟槽的半导体衬底上形成金属层; 去除所述金属层的部分以暴露所述介电层; 以及对所述金属层执行到预定目标的回蚀处理。