公开(公告)号：US20110148684A1

公开(公告)日：2011-06-23

申请号：US12970861

申请日：2010-12-16

申请人： Hyun Kyu Yu ,  Seon Ho Han ,  Young Hwa Kim ,  Seong Hwan Cho

发明人： Hyun Kyu Yu ,  Seon Ho Han ,  Young Hwa Kim ,  Seong Hwan Cho

IPC分类号： H03M1/38

CPC分类号： H03M1/46 ,  H03M1/827

摘要： There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.

摘要翻译： 提供了仅包括最小电容器以执行模数转换操作的逐次逼近模数转换器，从而使得可以具有非常强的工艺变化电阻特性，同时具有减小的电容和电路面积。 逐次逼近模数转换器可以包括提供参考电流的参考电流提供单元; 信号存储单元，存储通过对参考电流进行充电而产生的参考信号和从外部输入的输入信号; 比较单元，其比较所述参考信号和所述输入信号; 以及控制器，其基于所述比较单元的比较结果来控制所述参考电流供给单元，同时根据所述二进制码来改变提供给所述信号存储单元的参考电流的供给量。

公开(公告)号：US08274420B2

公开(公告)日：2012-09-25

申请号：US12970861

申请日：2010-12-16

申请人： Hyun Kyu Yu ,  Seon Ho Han ,  Young Hwa Kim ,  Seong Hwan Cho

发明人： Hyun Kyu Yu ,  Seon Ho Han ,  Young Hwa Kim ,  Seong Hwan Cho

IPC分类号： H03M1/38

CPC分类号： H03M1/46 ,  H03M1/827

摘要： There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.

摘要翻译： 提供了仅包括最小电容器以执行模数转换操作的逐次逼近模数转换器，从而使得可以具有非常强的工艺变化电阻特性，同时具有减小的电容和电路面积。 逐次逼近模数转换器可以包括提供参考电流的参考电流提供单元; 信号存储单元，存储通过对参考电流进行充电而产生的参考信号和从外部输入的输入信号; 比较单元，其比较所述参考信号和所述输入信号; 以及控制器，其基于所述比较单元的比较结果来控制所述参考电流供给单元，同时根据所述二进制码来改变提供给所述信号存储单元的参考电流的供给量。

公开(公告)号：US06668035B2

公开(公告)日：2003-12-23

申请号：US10179840

申请日：2002-06-24

申请人： Seon Ho Han ,  Jang Hong Choi ,  Jae Hong Jang ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Jang Hong Choi ,  Jae Hong Jang ,  Hyun Kyu Yu

IPC分类号： H03K2100

CPC分类号： H03M7/3022 ,  H03L7/1978

摘要： The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

摘要翻译： 本发明涉及一种delta-sigma分数型分频器的结构。 分频器结构增加了Δ-Σ调制器的外部输入值和输出值，以调制吞咽计数器的值。 因此，本发明可以提供一种Δ-Σ分数分频器，其结构简单，并且可以获得具有宽带频率混合能力的Δ-Σ模式的结构的效果。

公开(公告)号：US08344772B2

公开(公告)日：2013-01-01

申请号：US12956498

申请日：2010-11-30

申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/06

CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

公开(公告)号：US07884673B2

公开(公告)日：2011-02-08

申请号：US12423764

申请日：2009-04-14

申请人： Seon Ho Han ,  Cheon Soo Kim ,  Jae Young Kim ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Cheon Soo Kim ,  Jae Young Kim ,  Hyun Kyu Yu

IPC分类号： H03F3/04

CPC分类号： H03F1/26 ,  H03F1/565 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/36 ,  H03F2200/451

摘要： A wideband low-noise amplifier includes a source-degenerated common-source amplifier, a common-gate amplifier, and a matching frequency band determiner. The source-degenerated common-source amplifier is configured to amplify an input signal to output a first signal that is opposite in phase to the input signal. The common-gate amplifier is connected in parallel to the source-degenerated common-source amplifier to amplify the input signal to output a second signal that has the same phase as the input signal. The matching frequency band determiner is configured to isolate an input terminal of the source-degenerated common-source amplifier and an input terminal of the common-gate amplifier and determine a matching frequency band.

摘要翻译： 宽带低噪声放大器包括源极退化的共源放大器，共栅放大器和匹配的频带确定器。 源极退化的共源放大器被配置为放大输入信号以输出与输入信号相位相反的第一信号。 共栅放大器与源极简并公共源放大器并联连接，以放大输入信号以输出与输入信号具有相同相位的第二信号。 匹配频带确定器被配置为隔离源极退化的共源极放大器的输入端和公共栅极放大器的输入端，并确定匹配的频带。

公开(公告)号：US20100135446A1

公开(公告)日：2010-06-03

申请号：US12629684

申请日：2009-12-02

申请人： Seon Ho Han ,  Jae Hoon Shim ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Jae Hoon Shim ,  Hyun Kyu Yu

IPC分类号： H04B1/10

CPC分类号： H04B1/001 ,  H04B1/0025

摘要： A digital-intensive RF receiver including: a first filter unit configured to allow an RF signal of a pre-set frequency band among RF signals to pass therethrough; a low noise amplifier (LNA) configured to amplify the RF signal from the first filter unit such that the RF signal has a pre-set magnitude; a second filter unit configured to allow an RF signal of a pre-set frequency band among RF signals from the LNA to pass therethrough; a clock generation unit configured to generate a pre-set reference frequency signal and generate a sub-sampling clock having a pre-set frequency lower than an RF carrier frequency by using the reference frequency signal; a sub-sampling A/D conversion unit configured to A/D-convert the RF signal from the second filter unit into a digital signal according to the sub-sampling clock from the clock generation unit, divide the RF signal into a plurality of frequency bands and sub-sample them during the A/D conversion process and perform noise shaping by the sub-channels included in the RF signal; and a digital processing unit configured to process a digital signal from the sub-sampling A/D conversion unit according to a system clock generated by using the reference frequency signal from the clock generation unit.

摘要翻译： 一种数字密集RF接收机，包括：第一滤波器单元，被配置为允许RF信号中的预设频带的RF信号通过; 低噪声放大器（LNA），被配置为放大来自第一滤波器单元的RF信号，使得RF信号具有预设的幅度; 第二滤波器单元，被配置为允许来自所述LNA的RF信号中的预设频带的RF信号通过; 时钟生成单元，被配置为通过使用所述参考频率信号来生成预设参考频率信号并生成具有低于RF载波频率的预置频率的子采样时钟; 子采样A / D转换单元，被配置为根据来自时钟生成单元的子采样时钟将来自第二滤波器单元的RF信号进行A / D转换为数字信号，将RF信号分成多个频率 在A / D转换过程中对它们进行子采样，并通过RF信号中包含的子信道进行噪声整形; 以及数字处理单元，被配置为根据通过使用来自时钟生成单元的参考频率信号产生的系统时钟来处理来自子采样A / D转换单元的数字信号。

公开(公告)号：US20110148490A1

公开(公告)日：2011-06-23

申请号：US12956498

申请日：2010-11-30

申请人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Seon Ho Han ,  Mi Jeong Park ,  Jang Hong Choi ,  Seong Do Kim ,  Hyun Kyu Yu

IPC分类号： H03L7/08 ,  H03M1/50

CPC分类号： H03L7/095 ,  G04F10/005 ,  H03L7/085 ,  H03L7/103 ,  H03L2207/50

摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

摘要翻译： 全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

公开(公告)号：US07348849B2

公开(公告)日：2008-03-25

申请号：US11497461

申请日：2006-08-01

申请人： Seon Ho Han ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Hyun Kyu Yu

IPC分类号： H03F3/45 ,  H03G3/10

CPC分类号： H03G1/007 ,  H03F1/342 ,  H03F3/211 ,  H03F3/45206 ,  H03F3/45659 ,  H03F2200/15 ,  H03F2203/21154 ,  H03F2203/45008 ,  H03F2203/45302 ,  H03G7/06

摘要： A complementary metal oxide semiconductor (CMOS) variable gain amplifier has a wider decibel-linear gain variation characteristic with respect to a control voltage when a signal is amplified. The variable gain amplifier includes: a bias input circuit for supplying a current corresponding to a bias voltage; an operation region combination and feedback circuit connected to the bias input circuit and combining at least two amplifiers by feedback in response to a control voltage, each amplifier having a decibel-linear characteristic in saturation and triode regions of a complementary metal oxide semiconductor (CMOS); and a bias output circuit connected to the bias input circuit, and outputting bias current controlled by the operation region combination and feedback circuit.

摘要翻译： 互补金属氧化物半导体（CMOS）可变增益放大器在信号被放大时相对于控制电压具有更宽的分贝线性增益变化特性。 可变增益放大器包括：偏置输入电路，用于提供对应于偏置电压的电流; 连接到偏置输入电路的操作区域组合和反馈电路，并且通过响应于控制电压的反馈来组合至少两个放大器，每个放大器在互补金属氧化物半导体（CMOS）的饱和度和三极管区域中具有分贝线性特性， ; 以及偏置输出电路，连接到偏置输入电路，并输出由操作区域组合和反馈电路控制的偏置电流。

公开(公告)号：US20070132513A1

公开(公告)日：2007-06-14

申请号：US11497461

申请日：2006-08-01

申请人： Seon Ho Han ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Hyun Kyu Yu

IPC分类号： H03G3/10

CPC分类号： H03G1/007 ,  H03F1/342 ,  H03F3/211 ,  H03F3/45206 ,  H03F3/45659 ,  H03F2200/15 ,  H03F2203/21154 ,  H03F2203/45008 ,  H03F2203/45302 ,  H03G7/06

摘要： A complementary metal oxide semiconductor (CMOS) variable gain amplifier has a wider decibel-linear gain variation characteristic with respect to a control voltage when a signal is amplified. The variable gain amplifier includes: a bias input circuit for supplying a current corresponding to a bias voltage; an operation region combination and feedback circuit connected to the bias input circuit and combining at least two amplifiers by feedback in response to a control voltage, each amplifier having a decibel-linear characteristic in saturation and triode regions of a complementary metal oxide semiconductor (CMOS); and a bias output circuit connected to the bias input circuit, and outputting bias current controlled by the operation region combination and feedback circuit.

摘要翻译： 互补金属氧化物半导体（CMOS）可变增益放大器在信号被放大时相对于控制电压具有更宽的分贝线性增益变化特性。 可变增益放大器包括：偏置输入电路，用于提供对应于偏置电压的电流; 连接到偏置输入电路的操作区域组合和反馈电路，并且通过响应于控制电压的反馈来组合至少两个放大器，每个放大器在互补金属氧化物半导体（CMOS）的饱和度和三极管区域中具有分贝线性特性， ; 以及偏置输出电路，连接到偏置输入电路，并输出由操作区域组合和反馈电路控制的偏置电流。

公开(公告)号：US20100060363A1

公开(公告)日：2010-03-11

申请号：US12423764

申请日：2009-04-14

申请人： Seon Ho Han ,  Kim Cheon Soo ,  Kim Jae Young ,  Yu Hyun Kyu

发明人： Seon Ho Han ,  Kim Cheon Soo ,  Kim Jae Young ,  Yu Hyun Kyu

IPC分类号： H03F3/191

CPC分类号： H03F1/26 ,  H03F1/565 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/36 ,  H03F2200/451

摘要： A wideband low-noise amplifier includes a source-degenerated common-source amplifier, a common-gate amplifier, and a matching frequency band determiner. The source-degenerated common-source amplifier is configured to amplify an input signal to output a first signal that is opposite in phase to the input signal. The common-gate amplifier is connected in parallel to the source-degenerated common-source amplifier to amplify the input signal to output a second signal that has the same phase as the input signal. The matching frequency band determiner is configured to isolate an input terminal of the source-degenerated common-source amplifier and an input terminal of the common-gate amplifier and determine a matching frequency band.

摘要翻译： 宽带低噪声放大器包括源极退化的共源放大器，共栅放大器和匹配的频带确定器。 源极退化的共源放大器被配置为放大输入信号以输出与输入信号相位相反的第一信号。 共栅放大器与源极简并公共源放大器并联连接，以放大输入信号以输出与输入信号具有相同相位的第二信号。 匹配频带确定器被配置为隔离源极退化的共源极放大器的输入端和公共栅极放大器的输入端，并确定匹配的频带。