公开(公告)号：US08742478B2

公开(公告)日：2014-06-03

申请号：US13667097

申请日：2012-11-02

申请人： Hyun-jong Chung ,  U-in Chung ,  Ki-nam Kim

发明人： Hyun-jong Chung ,  U-in Chung ,  Ki-nam Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/772 ,  B82Y40/00 ,  H01L21/8232 ,  H01L27/0688 ,  H01L29/1606 ,  H01L29/41758 ,  H01L29/518 ,  H01L29/778 ,  H01L29/78606 ,  H01L29/78684 ,  Y10S977/734 ,  Y10S977/842 ,  Y10S977/938

摘要： A graphene transistor includes: a gate electrode on a substrate; a gate insulating layer on the gate electrode; a graphene channel on the gate insulating layer; a source electrode and a drain electrode on the graphene channel, the source and drain electrode being separate from each other; and a cover that covers upper surfaces of the source electrode and the drain electrode and forms an air gap above the graphene channel between the source electrode and the drain electrode.

摘要翻译： 石墨烯晶体管包括：基板上的栅电极; 栅电极上的栅极绝缘层; 栅极绝缘层上的石墨烯通道; 在石墨烯通道上的源极和漏极，源极和漏极彼此分离; 以及覆盖源电极和漏电极的上表面并在源电极和漏电极之间的石墨烯通道上方形成气隙的盖。

公开(公告)号：US08305816B2

公开(公告)日：2012-11-06

申请号：US12222895

申请日：2008-08-19

申请人： Ki-tae Park ,  Ki-nam Kim ,  Yeong-taek Lee

发明人： Ki-tae Park ,  Ki-nam Kim ,  Yeong-taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C2211/5621

摘要： A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells.

摘要翻译： 控制数据的方法包括：相对于与第一位线组对应的位线连接的非易失性存储单元，通过改变控制电压来首先控制写入非易失性存储单元的数据， 连接到与第二位线组对应的位线的非易失性存储单元，通过改变控制电压将第二控制数据写入非易失性存储单元。 控制可能包括阅读或验证。 在验证之前，该方法可以包括向非易失性存储器单元写入数据。

公开(公告)号：US07250335B2

公开(公告)日：2007-07-31

申请号：US11201803

申请日：2005-08-11

申请人： Won-suk Yang ,  Ki-nam Kim

发明人： Won-suk Yang ,  Ki-nam Kim

IPC分类号： H01L21/8239

CPC分类号： H01L21/76897

摘要： An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.

摘要翻译： 诸如存储器件的集成电路器件包括衬底以及衬底中的多行有源区域，有源区域以交错图案排列，使得第一行的有源区域与隔离的部分对准 分隔相邻第二行的有效区域的区域。 源极和漏极区域处于有源区域中并且被布置成使得每个有源区域包括设置在两个源极区域之间的漏极区域。 多个字线结构位于衬底上，横向于有源区的行布置，使得字线结构跨越源极区域和漏极区域之间的有源区域。 导电焊盘的各行布置在相应的相邻字线结构之间，包括源极区上的第一导电焊盘，漏极区上的第二导电焊盘以及分离有源区的隔离区上的第三导电。 多个位线结构在基板上，横向于字线结构延伸并与第二导电焊盘接触。 还描述了相关的制造方法。

公开(公告)号：US07164204B2

公开(公告)日：2007-01-16

申请号：US10770738

申请日：2004-02-03

申请人： Won-suk Yang ,  Ki-nam Kim

发明人： Won-suk Yang ,  Ki-nam Kim

IPC分类号： H01L23/52

CPC分类号： H01L24/02 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/30105

摘要： An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and an insulating region, a contact pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and having a contact hole for exposing both the contact pad and the auxiliary pad.

摘要翻译： 提供了当形成接触孔以露出接触焊盘时避免未对准的集成电路器件结构及其制造方法。 集成电路器件包括具有导电区域和绝缘区域的半导体衬底，半导体衬底的导电区域上的接触焊盘，与接触焊盘相邻的辅助焊盘以及半导体衬底上的层间绝缘层，并具有 用于露出接触垫和辅助垫的接触孔。

公开(公告)号：US20050272251A1

公开(公告)日：2005-12-08

申请号：US11201803

申请日：2005-08-11

申请人： Won-suk Yang ,  Ki-nam Kim

发明人： Won-suk Yang ,  Ki-nam Kim

IPC分类号： H01L21/768 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/76897

摘要： An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.

摘要翻译： 诸如存储器件的集成电路器件包括衬底以及衬底中的多行有源区域，有源区域以交错图案排列，使得第一行的有源区域与隔离的部分对准 分隔相邻第二行的有效区域的区域。 源极和漏极区域处于有源区域中并且被布置成使得每个有源区域包括设置在两个源极区域之间的漏极区域。 多个字线结构位于衬底上，横向于有源区的行布置，使得字线结构跨越源极区域和漏极区域之间的有源区域。 导电焊盘的相应行设置在相应的相邻字线结构之间，包括源区上的第一导电焊盘，漏极区上的第二导电焊盘以及分离有源区的隔离区上的第三导电。 多个位线结构在基板上，横向于字线结构延伸并与第二导电焊盘接触。 还描述了相关的制造方法。

公开(公告)号：US20050070094A1

公开(公告)日：2005-03-31

申请号：US10989930

申请日：2004-11-16

申请人： Won-suk Yang ,  Ki-nam Kim ,  Hong-sik Jeong

发明人： Won-suk Yang ,  Ki-nam Kim ,  Hong-sik Jeong

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a width of an entrance portion adjacent to the surface of the ILD layer larger than the width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a width larger than that of the second contact stud. The second contact stud has a width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad. The entrance portion of the first contact stud has a width about 30-60% larger than that of the contacting portion.

摘要翻译： 半导体器件及其制造方法包括半导体衬底，形成在半导体衬底上的层间电介质层（ILD）层，形成在ILD层中的第一接触柱，具有与ILD层的表面相邻的入口部分的宽度 大于邻近半导体衬底的接触部分的宽度;以及第二接触柱，其与第一接触螺柱间隔开并形成在ILD层中。 半导体器件还包括形成在ILD层上的接合焊盘，其接触第二接触柱的表面，其宽度大于第二接触柱的宽度。 第二接触柱具有与入口部相同的接触部的宽度。 此外，在着陆焊盘的侧壁上形成至少一个包括蚀刻阻挡材料的间隔物，并且在着陆焊盘上形成蚀刻停止层。 第一接触柱的入口部分的宽度比接触部分的宽度大30-60％。

公开(公告)号：US06852581B2

公开(公告)日：2005-02-08

申请号：US10266220

申请日：2002-10-08

申请人： Yoon-soo Chun ,  Dong-won Shin ,  Ki-nam Kim

发明人： Yoon-soo Chun ,  Dong-won Shin ,  Ki-nam Kim

IPC分类号： H01L27/108 ,  H01L21/338 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/088 ,  H01L31/0328

CPC分类号： H01L21/76837 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  Y10S257/90

摘要： According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.

摘要翻译： 根据本发明的实施例，提供了制造半导体器件的方法以及由此制造的半导体器件。 形成在半导体衬底中限定有源区的场区。 间隔开的栅极形成在半导体衬底的有源区上。 栅极具有远离半导体衬底延伸的侧壁。 第一间隔件形成在门的侧壁上。 第二间隔件形成在第一间隔件上并与栅极相对。 使用第一和第二间隔物作为离子注入掩模，将离子杂质注入到与栅极相邻的半导体衬底的有源区中。 第二间隔件的一部分被去除以加宽门之间的间隙。 在栅极之间的间隙中的半导体衬底上形成介电层。

公开(公告)号：US07482210B2

公开(公告)日：2009-01-27

申请号：US11370454

申请日：2006-03-07

申请人： Ji-young Kim ,  Ki-nam Kim

发明人： Ji-young Kim ,  Ki-nam Kim

IPC分类号： H01L21/84

CPC分类号： H01L21/823412 ,  H01L21/761 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the semiconductor substrate; a channel silicon layer arranged under the gate insulating layer to operate as a channel for connecting sources and drains; and buried junction isolation insulating layers under the channel silicon layer. The buried junction isolation insulating layers isolate source/drain junction regions of a MOS transistor, so that a short circuit in a bulk region under the channel of a transistor due to the high-integration of the device can be prevented.

摘要翻译： 提供了一种半导体器件及其制造方法。 所提供的半导体器件包括形成在半导体衬底中以限定有源区的场氧化物层; 形成在有源区上的栅极结构; 源极/漏极结形成在半导体衬底上的栅极结构的任一侧上; 布置在栅极绝缘层下方的沟道硅层，用作连接源极和漏极的沟道; 并在通道硅层下方埋入结隔离绝缘层。 掩埋结隔离绝缘层隔离MOS晶体管的源极/漏极结区域，从而可以防止由于器件的高集成度而在晶体管的沟道下面的体区域中的短路。

公开(公告)号：US07300888B2

公开(公告)日：2007-11-27

申请号：US10008700

申请日：2001-12-07

申请人： Hong-sik Jeong ,  Soo-ho Shin ,  Won-suk Yang ,  Ki-nam Kim

发明人： Hong-sik Jeong ,  Soo-ho Shin ,  Won-suk Yang ,  Ki-nam Kim

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/316 ,  H01L21/76895 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.

摘要翻译： 通过在基板上形成绝缘层来制造集成电路器件。 在绝缘层上形成覆盖层，并对覆盖层和绝缘层进行图案化。 绝缘垫片形成在绝缘层的侧壁上，使得绝缘隔离物，覆盖层和衬底包围绝缘层。

公开(公告)号：US07106617B2

公开(公告)日：2006-09-12

申请号：US11029616

申请日：2005-01-05

申请人： Byung-Gil Jeon ,  Ki-nam Kim

发明人： Byung-Gil Jeon ,  Ki-nam Kim

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices include a ferroelectric memory cell. The ferroelectric memory cell has at least one bit line and a plate line. A control circuit drives the at least one bit line with write data substantially concurrently with activation of the plate line during a write operation. The memory devices may also include a sense amplifier coupled to the ferroelectric memory cell and the control circuit may be further configured to deactivate the plate line substantially concurrently with activation of the sense amplifier during a read operation.