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    Method Of Manufacturing High Electron Mobility Transistor
    4.
    发明申请
    Method Of Manufacturing High Electron Mobility Transistor 有权
    制造高电子迁移率晶体管的方法

    公开(公告)号：US20110212582A1

    公开(公告)日：2011-09-01

    申请号：US13017361

    申请日：2011-01-31

    Applicant: Ki-ha Hong ,  U-in Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    Inventor： Ki-ha Hong ,  U-in Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    IPC: H01L21/335

    CPC classification number: H01L29/402 ,  H01L29/0891 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.

    Abstract translation: 制造高电子迁移率晶体管（HEMT）的方法可以包括在衬底上形成具有不同晶格常数的第一和第二材料层，在第二材料层上形成源极，漏极和栅极，以及改变第二材料层 在栅极和漏极之间形成不同的材料层，或改变第二材料层的厚度，或在第二材料层上形成p型半导体层。 第二材料层的变化可以在栅极和漏极之间的第二材料层的整个区域中发生，或者仅在与栅极相邻的第二材料层的部分区域中发生。 p型半导体层可以形成在栅极和漏极之间的第二材料层的整个顶表面上，或者仅形成在与栅极相邻的顶表面的部分区域上。

    Semiconductor structures including accumulations of silicon boronide and related methods
    5.
    发明申请
    Semiconductor structures including accumulations of silicon boronide and related methods 审中-公开
    半导体结构包括硅化硼的积累和相关方法

    公开(公告)号：US20070215959A1

    公开(公告)日：2007-09-20

    申请号：US11713877

    申请日：2007-03-05

    Applicant: Jin-Wook Lee ,  Chang-Woo Ryoo ,  Tai-Su Park ,  U-In Chung ,  Yu-Gyun Shin

    Inventor： Jin-Wook Lee ,  Chang-Woo Ryoo ,  Tai-Su Park ,  U-In Chung ,  Yu-Gyun Shin

    IPC: H01L29/94

    CPC classification number: H01L29/4941 ,  H01L21/28061

    Abstract: A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.

    Abstract translation: 半导体器件可以包括半导体衬底，半导体衬底的表面上的第一和第二源极/漏极区域以及在第一和第二源极/漏极区域之间具有沟道区域的半导体衬底的表面上的沟道区域。 绝缘层图案可以在沟道区上，第一导电层图案可以在绝缘层上，并且第二导电层图案可以在第一导电层图案上。 绝缘层图案可以在第一导电层图案和沟道区之间，并且第一导电层图案可以包括硼掺杂多晶硅，表面部分具有硅化硼的积累。 第一导电层图案可以在第二导电层图案和绝缘层图案之间，并且第二导电层图案可以包括钨。 还讨论了相关方法。

    Vertical channel field effect transistors having insulating layers thereon
    7.
    发明授权
    Vertical channel field effect transistors having insulating layers thereon 有权
    其上具有绝缘层的垂直沟道场效应晶体管

    公开(公告)号：US07148541B2

    公开(公告)日：2006-12-12

    申请号：US10780067

    申请日：2004-02-17

    Applicant: Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    Inventor： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    IPC: H01L27/01

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

    Abstract: A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

    Abstract translation: 场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝向衬底延伸到源极/漏极 区域交界处 晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极 侧壁朝向衬底以超出源/漏区结。 还公开了相关方法。

    METHODS OF FABRICATING VERTICAL CHANNEL FIELD EFFECT TRANSISTORS HAVING INSULATING LAYERS THEREON
    8.
    发明申请
    METHODS OF FABRICATING VERTICAL CHANNEL FIELD EFFECT TRANSISTORS HAVING INSULATING LAYERS THEREON 有权
    制造具有绝缘层的垂直通道场效应晶体管的方法

    公开(公告)号：US20070066018A1

    公开(公告)日：2007-03-22

    申请号：US11556804

    申请日：2006-11-06

    Applicant: Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    Inventor： Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    IPC: H01L21/336

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

    Abstract: A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

    Abstract translation: 形成场效应晶体管的方法包括形成从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，并且形成在垂直沟道的侧壁上朝向衬底延伸的绝缘层， 超出源/漏区结。 该方法还可以包括在侧壁上形成远离衬底延伸到绝缘层的氮化物层，形成在侧壁上延伸的第二绝缘层，所述第二绝缘层通过氮化物层从沟道分离，并形成栅电极 在侧壁上朝向衬底延伸超过源/漏区结。

    Wire forming method for semiconductor device
    9.
    发明授权
    Wire forming method for semiconductor device 失效
    半导体器件的成线方法

    公开(公告)号：US5604156A

    公开(公告)日：1997-02-18

    申请号：US560913

    申请日：1995-11-20

    Applicant: U-in Chung ,  Jae-duk Kim ,  Chang-ki Hong

    Inventor： U-in Chung ,  Jae-duk Kim ,  Chang-ki Hong

    IPC: H01L21/28 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L21/44

    CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/5329 ,  H01L2924/0002

    Abstract: A wire forming method for a semiconductor device includes the steps of depositing an insulation material on a semiconductor substrate and patterning the insulation material to form a first insulation layer, forming a lower capping layer on the first insulation layer, etching the lower capping layer and the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate, forming a wire layer over the capping layer and the first part of the semiconductor substrate, performing a chemical and mechanical polishing (CMP) process with respect to the wire layer and the lower capping layer to expose the first insulation layer, forming a second insulation layer over the wire layer and the first insulation layer, and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate. The wire forming method can prevent the lifting of the wire layer, the splitting of the lower insulation layer, and the formation of a protrusion n the second contact hole.

    Abstract translation: 一种用于半导体器件的线形成方法包括以下步骤：在半导体衬底上沉积绝缘材料并图案化绝缘材料以形成第一绝缘层，在第一绝缘层上形成下覆盖层，蚀刻下封盖层和 第一绝缘层以形成暴露半导体衬底的第一部分的第一接触孔，在覆盖层和半导体衬底的第一部分上方形成引线层，对相对于第二绝缘层进行化学和机械抛光（CMP）处理 线层和下覆盖层以暴露第一绝缘层，在导线层和第一绝缘层上形成第二绝缘层，并蚀刻第一和第二绝缘层以形成第二接触孔，其暴露第二绝缘层的第二部分 半导体衬底。 线形成方法可以防止线层的提升，下绝缘层的分离，以及在第二接触孔处形成突起。

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