Abstract:
A METHOD FOR FABRICATING DIELECTRIC ISOLATED INTEGRATED DEVICES WHICH ALLOWS THE OF FORMATION OF A TRULY PLANAR SURFACE. THE METHOD INCLUDES ETCHING ISOLATION CHANNELS IN A SEMICONDUCTOR SUBSTRATE THROUGH A SUITABLE MASK. THE MASK PATTERN IS DESIGNED TO ENHANCE DEEPER ETCHING AT CERTAIN LOCATIONS IN THE ISOLATION CHANNELS. A DIELECTRIC LAYER IS FORMED OVER THE EXPOSED SURFACES OF THE ISOLATION CHANNELS AND A SEMICONDUCTOR MATERIAL IS GROWN IN THE CHANNELS. THE DEEPER ETCHED LOCATIONS WHICH ARE NOW FILLED WITH DIELECTRIC ISOLATION ARE USED AS A DEPTH GUIDE IN THE FORMATION OF A DIELECTRIC LAYER FROM THE SEMICONDUCTOR SUBSTRATE SURFACE OPPOSITE TO THE ONE FROM WHICH THE ETCHING TOOK PLACE. THE DEPTH GUIDE CAN BE USED IN EITHER A DEEP ETCH OR LAP-BACK PROCESS. THE LAST ISOLATION STEP IS THEN TO CONTINUE THE DIELECTRIC LAYER PAST THE DEPTH GUIDE TO THE MAJOR PORTION OF TSHE ISOLATION CHANNELS TO PRODUCE THE FULLY ISOLATED ISLANDS OF SEMICONDUCTOR MATERIAL IN THE SEMICONDUCTOR SUBSTRATE.
Abstract:
A read only memory having the capability of being written into once after manufacture. The cells of the memory are capable of being fused or permanently altered by directing a fusing current to the selected cells. The cell is a monolithic semiconductor device comprising a diode to be biased in a forward direction and a diode to be biased in the reverse direction structured so as to form back-to-back diodes. The reverse diode has a lower reverse breakdown voltage than the forward diode, and a metal connection, unconnected to any remaining circuit elements contacts the semiconductor device between diode junctions. The fusing current causes a metal-semiconductor alloy to form and short out the reverse diode.