公开(公告)号：US11040872B2

公开(公告)日：2021-06-22

申请号：US16595532

申请日：2019-10-08

Applicant: Infineon Technologies AG

Inventor： Claus Waechter ,  Edward Fuergut ,  Bernd Goller ,  Michael Ledutke ,  Dominic Maier

IPC: H01L27/14 ,  B81C1/00 ,  B81B7/00

Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

公开(公告)号：US09698070B2

公开(公告)日：2017-07-04

申请号：US13860679

申请日：2013-04-11

Applicant: Infineon Technologies AG

Inventor： Michael Ledutke ,  Edward Fuergut

IPC: H01L23/28 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L21/673

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/67336 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.

公开(公告)号：US10361138B2

公开(公告)日：2019-07-23

申请号：US15607735

申请日：2017-05-30

Applicant: Infineon Technologies AG

Inventor： Michael Ledutke ,  Edward Fuergut

IPC: H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L21/673

Abstract: In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.

公开(公告)号：US10128165B2

公开(公告)日：2018-11-13

申请号：US15796771

申请日：2017-10-28

Applicant: Infineon Technologies AG

Inventor： Wolfram Hable ,  Andreas Grassmann ,  Juergen Hoegerl ,  Eduard Knauer ,  Michael Ledutke

IPC: H01L23/28 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L25/00 ,  B60L11/18 ,  H02M7/00

Abstract: A package comprising at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, a first electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one first terminal of at least one of the at least one electronic chip, and a second electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one second terminal of at least one of the at least one electronic chip, wherein at least a portion of the first electrically conductive contact structure and at least a portion of the second electrically conductive contact structure within the encapsulant are spaced in a direction between two opposing main surfaces of the package.

公开(公告)号：US12062589B2

公开(公告)日：2024-08-13

申请号：US17361823

申请日：2021-06-29

Applicant: Infineon Technologies AG

Inventor： Adrian Lis ,  Michael Ledutke

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H05K7/14

CPC classification number: H01L23/3675 ,  H01L21/4871 ,  H01L23/3735 ,  H01L23/42

Abstract: One example of a semiconductor package includes a first substrate, a second substrate, a semiconductor die, and a spacer. The semiconductor die is attached to the first substrate. The spacer is attached to the semiconductor die and attached to the second substrate via solder. A surface of the second substrate facing the spacer includes a plurality of recesses extending from proximate at least one edge of the spacer to contain a portion of the solder.

公开(公告)号：US10923364B2

公开(公告)日：2021-02-16

申请号：US16118651

申请日：2018-08-31

Applicant: Infineon Technologies AG

Inventor： Kristina Mayer ,  Michael Ledutke ,  Johannes Lodermeyer

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A method comprises: arranging a plurality of semiconductor chips above a carrier, wherein active main surfaces of the semiconductor chips face the carrier; filling a cavity with a molding material; pressing the semiconductor chips arranged on the carrier into the molding material; and separating the molding material with the semiconductor chips embedded therein from the carrier, wherein main surfaces of the semiconductor chips that are situated opposite the active main surfaces are covered by the molding material.

公开(公告)号：US09202753B2

公开(公告)日：2015-12-01

申请号：US13754382

申请日：2013-01-30

Applicant: Infineon Technologies AG

Inventor： Johann Kosub ,  Michael Ledutke

IPC: H01L29/06 ,  H01L21/78 ,  H01L21/02 ,  H01L23/32 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/02697 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/014

Abstract: A method includes applying a reinforcing wafer to a semiconductor wafer, thereby forming a composite wafer. Further the method includes dividing the composite wafer, thereby generating a plurality of composite chips each including a semiconductor chip and a reinforcing chip.

Abstract translation: 一种方法包括将加强晶片应用于半导体晶片，由此形成复合晶片。 此外，该方法包括分割复合晶片，从而生成各自包括半导体芯片和增强芯片的多个复合芯片。

公开(公告)号：US20220415732A1

公开(公告)日：2022-12-29

申请号：US17840971

申请日：2022-06-15

Applicant: Infineon Technologies AG

Inventor： Christoph Liebl ,  Stefan Schwab ,  Adrian Lis ,  Michael Ledutke ,  Lisa Aschenbrenner

IPC: H01L23/057 ,  H01L23/31 ,  H01L23/373

Abstract: A semiconductor module includes: a chip carrier having a first side and a second, opposite side; a semiconductor chip arranged on the first side of the chip carrier; an encapsulation body that encapsulates the semiconductor chip; and at least two external contacts made of a metal or an alloy and arranged next to each other, which are electrically and mechanically connected to the first side of the first chip carrier and protrude laterally out of the encapsulation body. At least one of the external contacts has at least one wing arranged within the encapsulation body and located opposite the other external contact. The wing includes one or more cutouts that are filled with the encapsulation material of the encapsulation body.

公开(公告)号：US20180022601A1

公开(公告)日：2018-01-25

申请号：US15651522

申请日：2017-07-17

Applicant: Infineon Technologies AG

Inventor： Claus Waechter ,  Edward Fuergut ,  Bernd Goller ,  Michael Ledutke ,  Dominic Maier

IPC: B81C1/00 ,  B81B7/00

Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.

公开(公告)号：US20140210054A1

公开(公告)日：2014-07-31

申请号：US13754382

申请日：2013-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Johann Kosub ,  Michael Ledutke

IPC: H01L21/78 ,  H01L21/02 ,  H01L23/498 ,  H01L23/32

CPC classification number: H01L21/78 ,  H01L21/02697 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/014

Abstract: A method includes applying a reinforcing wafer to a semiconductor wafer, thereby forming a composite wafer. Further the method includes dividing the composite wafer, thereby generating a plurality of composite chips each including a semiconductor chip and a reinforcing chip.

Abstract translation: 一种方法包括将加强晶片应用于半导体晶片，由此形成复合晶片。 此外，该方法包括分割复合晶片，从而生成各自包括半导体芯片和增强芯片的多个复合芯片。