公开(公告)号：US20190311966A1

公开(公告)日：2019-10-10

申请号：US16379289

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/532 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L21/56

Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

公开(公告)号：US09595469B2

公开(公告)日：2017-03-14

申请号：US14071076

申请日：2013-11-04

Applicant: Infineon Technologies AG

Inventor： Jochen Hilsenbeck ,  Jens Peter Konrath ,  Stefan Krivec

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/16 ,  H01L29/808 ,  H01L29/10 ,  H01L23/00 ,  H01L21/285 ,  H01L29/20

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/28575 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/532 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/8083 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05188 ,  H01L2224/05551 ,  H01L2224/05561 ,  H01L2224/05566 ,  H01L2224/05599 ,  H01L2224/05688 ,  H01L2224/45099 ,  H01L2224/85375 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/0496 ,  H01L2924/01042 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

Abstract translation: 半导体器件包括具有正面和背面的半导体本体，具有位于前表面的有源区，前表面金属化层具有指向有源区的正面和背面，前表面金属化层 设置在半导体本体的前表面上并与活性区电连接，以及位于活性区和金属化层之间的包括无定形氮化钼的第一阻挡层。 此外，提供了一种用于制造这种装置的方法。

公开(公告)号：US20150123149A1

公开(公告)日：2015-05-07

申请号：US14532129

申请日：2014-11-04

Applicant: Infineon Technologies AG

Inventor： Jochen Hilsenbeck ,  Jens Peter Konrath ,  Stefan Krivec

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32133 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/53238 ,  H01L24/05 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/8083 ,  H01L2224/022 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/85375 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/0001 ,  H01L2924/00014

Abstract: A semiconductor device comprises a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, comprising amorphous metal nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

Abstract translation: 半导体器件包括具有前表面和后表面的半导体本体，具有位于前表面的有源区，前表面金属化层具有指向有源区的正面和背面，前表面金属化层 设置在半导体主体的前表面上并且电连接到有源区，以及第一阻挡层，包括位于有源区和金属化层之间的非晶金属氮化物。 此外，提供了一种用于制造这种装置的方法。

公开(公告)号：US11798807B2

公开(公告)日：2023-10-24

申请号：US17315943

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Stefan Krivec ,  Ronny Kern ,  Stefan Kramp ,  Gregor Langer ,  Hannes Winkler ,  Stefan Woehlert

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L21/0485 ,  H01L21/02068 ,  H01L29/1608 ,  H01L29/45

Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

公开(公告)号：US11217500B2

公开(公告)日：2022-01-04

申请号：US16379289

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

公开(公告)号：US20150123145A1

公开(公告)日：2015-05-07

申请号：US14071076

申请日：2013-11-04

Applicant: Infineon Technologies AG

Inventor： Jochen Hilsenbeck ,  Jens Peter Konrath ,  Stefan Krivec

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/28575 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/532 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/8083 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05188 ,  H01L2224/05551 ,  H01L2224/05561 ,  H01L2224/05566 ,  H01L2224/05599 ,  H01L2224/05688 ,  H01L2224/45099 ,  H01L2224/85375 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/0496 ,  H01L2924/01042 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

Abstract translation: 半导体器件包括具有正面和背面的半导体本体，具有位于前表面的有源区，前表面金属化层具有指向有源区的正面和背面，前表面金属化层 设置在半导体本体的前表面上并与活性区电连接，以及位于活性区和金属化层之间的包括无定形氮化钼的第一阻挡层。 此外，提供了一种用于制造这种装置的方法。

公开(公告)号：US20190385842A1

公开(公告)日：2019-12-19

申请号：US16426051

申请日：2019-05-30

Applicant: Infineon Technologies AG

Inventor： Joachim Hirschler ,  Georg Ehrentraut ,  Christoffer Erbert ,  Klaus Goeschl ,  Markus Heinrici ,  Michael Hutzler ,  Wolfgang Koell ,  Stefan Krivec ,  Ingmar Neumann ,  Mathias Plappert ,  Michael Roesner ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/18 ,  H01L29/49 ,  H01L29/51

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

公开(公告)号：US09997459B2

公开(公告)日：2018-06-12

申请号：US15427428

申请日：2017-02-08

Applicant: Infineon Technologies AG

Inventor： Jochen Hilsenbeck ,  Jens Peter Konrath ,  Stefan Krivec

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/20 ,  H01L29/16

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/28575 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/532 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/8083 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05188 ,  H01L2224/05551 ,  H01L2224/05561 ,  H01L2224/05566 ,  H01L2224/05599 ,  H01L2224/05688 ,  H01L2224/45099 ,  H01L2224/85375 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/0496 ,  H01L2924/01042 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a semiconductor body having a front face, a back face and an active zone at the front face. A front surface metallization layer having a front face and a back face is disposed over the semiconductor body so that the back face of the front surface metallization layer faces the front face of the semiconductor body and is electrically connected to the active zone. An upper barrier layer made of amorphous molybdenum nitride is disposed on the front face of the front surface metallization layer.

公开(公告)号：US20160211140A1

公开(公告)日：2016-07-21

申请号：US14997221

申请日：2016-01-15

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Ronny Kern ,  Stefan Krivec ,  Ulrich Schmid ,  Laura Stoeber

IPC: H01L21/285 ,  H01L21/265 ,  H01L29/47

CPC classification number: H01L21/28537 ,  H01L21/02046 ,  H01L21/02049 ,  H01L21/0455 ,  H01L21/0495 ,  H01L21/2236 ,  H01L21/2652 ,  H01L21/67115 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/36 ,  H01L29/365 ,  H01L29/401 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/66848 ,  H01L29/872

Abstract: A method for processing a semiconductor includes irradiating a surface of a semiconductor with ions of a first gas type for cleaning the surface and implanting of ions of a second gas type in a region below the surface of the semiconductor for creating defects in the region below the surface. The irradiating and the implanting are performed within the same chamber.

Abstract translation: 一种用于处理半导体的方法包括用半导体的表面照射用于清洁表面的第一气体类型的离子和将第二气体类型的离子注入到半导体表面下方的区域中，用于在低于该半导体区域的区域内产生缺陷 表面。 照射和植入在相同的室内进行。

公开(公告)号：US20230420257A1

公开(公告)日：2023-12-28

申请号：US18240520

申请日：2023-08-31

Applicant: Infineon Technologies AG

Inventor： Stefan Krivec ,  Ronny Kern ,  Stefan Kramp ,  Gregor Langer ,  Hannes Winkler ,  Stefan Woehlert

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L21/0485 ,  H01L29/1608 ,  H01L29/45 ,  H01L21/02068

Abstract: A chip is provided. In an embodiment, the chip includes a silicon carbide substrate, a first sputtered metal layer on the silicon carbide substrate, and at least one second sputtered metal layer on the first sputtered metal layer. The first sputtered metal layer and the at least one second sputtered metal layer form an electrical contact. In another embodiment, the chip includes a silicon carbide substrate, a nickel-silicon layer on the silicon carbide substrate, and a layer sequence including a titanium layer, a nickel-containing layer, and a gold-tin or silver layer on the nickel-silicon layer.