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    Techniques for dynamic database access modes
    1.
    发明授权
    Techniques for dynamic database access modes 有权

    公开(公告)号：US11500825B2

    公开(公告)日：2022-11-15

    申请号：US16105031

    申请日：2018-08-20

    Applicant: INTEL CORPORATION

    Inventor： Ren Wang ,  Bruce Richardson ,  Tsung-Yuan Tai ,  Yipeng Wang ,  Pablo De Lara Guarch

    IPC: G06F16/21 ,  G06F16/22

    Abstract: Techniques and apparatus for dynamic data access mode processes are described. In one embodiment, for example, an apparatus may a processor, at least one memory coupled to the processor, the at least one memory comprising an indication of a database and instructions, the instructions, when executed by the processor, to cause the processor to determine a database utilization value for a database, perform a comparison of the database utilization value to at least one utilization threshold, and set an active data access mode to one of a low-utilization data access mode or a high-utilization data access mode based on the comparison. Other embodiments are described.

    TECHNOLOGIES FOR BUFFERING RECEIVED NETWORK PACKET DATA
    4.
    发明申请
    TECHNOLOGIES FOR BUFFERING RECEIVED NETWORK PACKET DATA 审中-公开

    公开(公告)号：US20190044893A1

    公开(公告)日：2019-02-07

    申请号：US16024774

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Bruce Richardson ,  Chris MacNamara ,  Patrick Fleming ,  Tomasz Kantecki ,  Ciara Loftus ,  John J. Browne ,  Patrick Connor

    IPC: H04L12/861 ,  H04L12/879

    Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.

    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS
    5.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS 审中-公开

    公开(公告)号：US20190041957A1

    公开(公告)日：2019-02-07

    申请号：US15951391

    申请日：2018-04-12

    Applicant: Intel Corporation

    Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

    IPC: G06F1/32

    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

    Packet flow classification
    6.
    发明授权
    Packet flow classification 有权

    公开(公告)号：US09769290B2

    公开(公告)日：2017-09-19

    申请号：US14286975

    申请日：2014-05-23

    Applicant: Intel Corporation

    Inventor： Cristian Florin F. Dumitrescu ,  Namakkal N. Venkatesan ,  Pierre Laurent ,  Bruce Richardson

    IPC: H04L12/743 ,  H04L29/06 ,  H04L12/64

    CPC classification number: H04L69/22 ,  H04L12/6418 ,  H04L45/7453

    Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.

    Technologies for demoting cache lines to shared cache
    8.
    发明授权
    Technologies for demoting cache lines to shared cache 有权

    公开(公告)号：US10657056B2

    公开(公告)日：2020-05-19

    申请号：US16024773

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC: G06F12/084 ,  G06F12/1072 ,  H04L12/933 ,  G06F12/128 ,  G06F13/28

    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

    Packet flow classification
    9.
    发明授权
    Packet flow classification 有权

    公开(公告)号：US10455063B2

    公开(公告)日：2019-10-22

    申请号：US15677564

    申请日：2017-08-15

    Applicant: Intel Corporation

    Inventor： Cristian Florin F. Dumitrescu ,  Namakkal N. Venkatesan ,  Pierre Laurent ,  Bruce Richardson

    IPC: H04L29/06 ,  H04L12/743 ,  H04L12/64

    Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.

    TECHNOLOGIES FOR USING A HARDWARE QUEUE MANAGER AS A VIRTUAL GUEST TO HOST NETWORKING INTERFACE
    10.
    发明申请
    TECHNOLOGIES FOR USING A HARDWARE QUEUE MANAGER AS A VIRTUAL GUEST TO HOST NETWORKING INTERFACE 审中-公开

    公开(公告)号：US20190044892A1

    公开(公告)日：2019-02-07

    申请号：US16144146

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： John Mangan ,  Niall D. McDonnell ,  Harry Van Haaren ,  Bruce Richardson ,  Ciara Loftus

    IPC: H04L12/883 ,  H04L12/935 ,  H04L12/931 ,  G06F9/455

    Abstract: Technologies for using a hardware queue manager as a virtual guest to host networking interface include a compute node configured to receive a pointer corresponding to each of one or more available receive buffers from a guest processor core of at least one processor of the compute node that has been allocated to a virtual guest managed by the compute node. The compute node is further configured to enqueue the received pointer of each of the one or more available receive buffers into an available buffer queue and facilitate access to the available receive buffers to at least a portion of a plurality of virtual switch processor cores. Each of the virtual switch processor cores comprises another processor core of the plurality of processor cores that has been allocated to a virtual switch of the compute node. Other embodiments are described herein.

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