公开(公告)号：US20240213250A1

公开(公告)日：2024-06-27

申请号：US18088547

申请日：2022-12-24

Applicant: INTEL CORPORATION

Inventor： Shao Ming KOH ,  Sudipto NASKAR ,  Leonard P. GULER ,  Patrick MORROW ,  Richard E. SCHENKER ,  Walid M. HAFEZ ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Jeanne L. LUCE ,  Dan S. LAVRIC ,  Jack T. KAVALIEROS ,  Matthew PRINCE ,  Lars LIEBMANN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/78696

Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned backbones. In an example, an integrated circuit structure includes a backbone including a lower backbone portion distinct from an upper backbone portion. A first vertical stack of nanowires is in lateral contact with a first side of the backbone. A second vertical stack of nanowires is in lateral contact with a second side of the backbone, the second side opposite the first side.

公开(公告)号：US20240312996A1

公开(公告)日：2024-09-19

申请号：US18121724

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Shao Ming KOH ,  Anand S. MURTHY ,  Mauro J. KOBRINSKY

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut with pyramidal channel structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires having a pyramidal profile with a pyramid angle. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure has a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires.

公开(公告)号：US20250105148A1

公开(公告)日：2025-03-27

申请号：US18372970

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Marvin PAIK ,  June CHOI ,  Shao Ming KOH ,  Supanee SUKRITTANON ,  Ananya DUTTA ,  Sudipto NASKAR

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines on a same level and along a same direction, a first one of the plurality of conductive lines having a first width and a first composition, and a second one of the plurality of conductive lines having a second width and a second composition. The second width greater than the first width, and the second composition is different than the first composition. The second one of the plurality of conductive lines has an uppermost surface above an uppermost surface of the first one of the plurality of conductive lines.

公开(公告)号：US20240312991A1

公开(公告)日：2024-09-19

申请号：US18121720

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Shao Ming KOH ,  David J. TOWNER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having tuned upper nanowires are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a first dipole material. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric including a second dipole material, wherein the second dipole material has a greater number of layers than the first dipole material or wherein the second dipole material does not include the first dipole material.

公开(公告)号：US20250006787A1

公开(公告)日：2025-01-02

申请号：US18215748

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Shao Ming KOH ,  Sean PURSEL ,  Charles H. WALLACE ,  Hongqian SUN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit structure includes a first vertical stack of horizontal nanowires or a first fin having a first lateral width. A first gate electrode is over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width. A second vertical stack of horizontal nanowires or a second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the second fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width, the third lateral width less than the first lateral width. A second gate electrode is over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced apart from the first gate electrode, and the second gate electrode having a fourth lateral width, the fourth lateral width less than the second lateral width.

公开(公告)号：US20240312986A1

公开(公告)日：2024-09-19

申请号：US18121731

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Shao Ming KOH ,  Sudipto NASKAR ,  Anand S. MURTHY ,  Nikhil MEHTA ,  Leonard P. GULER

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823842 ,  H01L27/0886 ,  H01L27/092

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut are described. For example, an integrated circuit structure includes a gate electrode over a vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. First and second dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure. The gate electrode has a zero edge placement error between the first dielectric cut plug structure and the second dielectric cut plug structure. An epitaxial source or drain structure is at an end of the vertical stack of horizontal nanowires and beneath the conductive trench contact.

公开(公告)号：US20240113233A1

公开(公告)日：2024-04-04

申请号：US17958290

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Shengsi LIU ,  Shao Ming KOH ,  Tahir GHANI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/785

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for techniques for creating a wall within a forkFET transistor structure, where the wall is adjacent to a first stack of nanoribbons on a first side of the wall and a second stack of nanoribbons on a second side of the wall opposite the first side of the wall. In embodiments, the wall extends beyond the top of the first stack of nanoribbons and electrically isolates a first gate metal coupled with the first stack of nanoribbons and a second gate metal coupled with the second stack of nanoribbons from each other. Other embodiments may be described and/or claimed.