公开(公告)号：US20230317809A1

公开(公告)日：2023-10-05

申请号：US17710791

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Shaun MILLS ,  Mauro J. KOBRINSKY

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/41733

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, the semiconductor device comprises a substrate, and a non-planar transistor with a source and a drain over the substrate. In an embodiment, a backside contact is provided to the source or drain through the substrate. In an embodiment, a residual liner is between the source or drain and the backside contact. In an embodiment, the residual liner does not extend entirely across an interface between the backside contact and the source or drain.

公开(公告)号：US20200006138A1

公开(公告)日：2020-01-02

申请号：US16024692

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Miriam RESHOTKO ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US20190035677A1

公开(公告)日：2019-01-31

申请号：US16070172

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Richard E. SCHENKER ,  Hui Jae YOO ,  Kevin L. LIN ,  Jasmeet S. CHAWLA ,  Stephanie A. BOJARSKI ,  Satyarth SURI ,  Colin T. CARVER ,  Sudipto NASKAR

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53271

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

公开(公告)号：US20250105148A1

公开(公告)日：2025-03-27

申请号：US18372970

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Marvin PAIK ,  June CHOI ,  Shao Ming KOH ,  Supanee SUKRITTANON ,  Ananya DUTTA ,  Sudipto NASKAR

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines on a same level and along a same direction, a first one of the plurality of conductive lines having a first width and a first composition, and a second one of the plurality of conductive lines having a second width and a second composition. The second width greater than the first width, and the second composition is different than the first composition. The second one of the plurality of conductive lines has an uppermost surface above an uppermost surface of the first one of the plurality of conductive lines.

公开(公告)号：US20210305358A1

公开(公告)日：2021-09-30

申请号：US16828497

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200090987A1

公开(公告)日：2020-03-19

申请号：US16604681

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Sudipto NASKAR ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: Passivating silicide-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. Each of the plurality of conductive lines is recessed relative to an uppermost surface of the ILD layer. A metal silicide layer is on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the metal silicide layer and on the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of the metal silicide layer on one of the plurality of conductive lines.

公开(公告)号：US20240312986A1

公开(公告)日：2024-09-19

申请号：US18121731

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Shao Ming KOH ,  Sudipto NASKAR ,  Anand S. MURTHY ,  Nikhil MEHTA ,  Leonard P. GULER

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823842 ,  H01L27/0886 ,  H01L27/092

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut are described. For example, an integrated circuit structure includes a gate electrode over a vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. First and second dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure. The gate electrode has a zero edge placement error between the first dielectric cut plug structure and the second dielectric cut plug structure. An epitaxial source or drain structure is at an end of the vertical stack of horizontal nanowires and beneath the conductive trench contact.

公开(公告)号：US20220238376A1

公开(公告)日：2022-07-28

申请号：US17720152

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Miriam RESHOTKO ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US20190385897A1

公开(公告)日：2019-12-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Sudipto NASKAR ,  Stephanie A. BOJARSKI ,  Kevin LIN ,  Marie KRYSAK ,  Tristan A. TRONIC ,  Hui Jae YOO ,  Jeffery D. BIELEFELD ,  Jessica M. TORRES

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.

公开(公告)号：US20240006512A1

公开(公告)日：2024-01-04

申请号：US17853500

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Walter CASPER, IV ,  Sudipto NASKAR ,  Marci Kahiehie Mi Hyon KANG ,  Weimin HAN ,  Vivek THIRTHA ,  Jianqiang LIN

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/6656 ,  H01L21/0228 ,  H01L29/0669 ,  H01L29/0847

Abstract: Embodiments disclosed herein include a transistor and methods of making a transistor. In an embodiment, the transistor comprises a channel region and a gate structure over the channel region. In an embodiment, a first spacer is on a first end of the gate structure, and a second spacer is on a second end of the gate structure. In an embodiment, individual ones of the first spacer and the second spacer comprise a first layer with a first dielectric constant, and a second layer with a second dielectric constant that is higher than the first dielectric constant. In an embodiment, the transistor further comprises a source region adjacent to the first spacer, and a drain region adjacent to the second spacer.