公开(公告)号：US20190252313A1

公开(公告)日：2019-08-15

申请号：US16318643

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Jessica M. TORRES ,  Jeffery D. BIELEFELD ,  Mauro J. KOBRINSKY ,  Christopher J. JEZEWSKI ,  Gopinath BHIMARASETTI

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L23/5226 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2221/1047

Abstract: Pore-filled dielectric materials for semiconductor structure fabrication, and methods of fabricating pore-filled dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a pore-filled dielectric material for semiconductor structure fabrication includes forming a trench in a material layer. The method also includes filling the trench with a porous dielectric material using a spin-on deposition process. The method also includes filling pores of the porous dielectric material with a metal-containing material using an atomic layer deposition (ALD) process.

公开(公告)号：US20190385897A1

公开(公告)日：2019-12-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Sudipto NASKAR ,  Stephanie A. BOJARSKI ,  Kevin LIN ,  Marie KRYSAK ,  Tristan A. TRONIC ,  Hui Jae YOO ,  Jeffery D. BIELEFELD ,  Jessica M. TORRES

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.