公开(公告)号：US20190252313A1

公开(公告)日：2019-08-15

申请号：US16318643

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Jessica M. TORRES ,  Jeffery D. BIELEFELD ,  Mauro J. KOBRINSKY ,  Christopher J. JEZEWSKI ,  Gopinath BHIMARASETTI

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L23/5226 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2221/1047

Abstract: Pore-filled dielectric materials for semiconductor structure fabrication, and methods of fabricating pore-filled dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a pore-filled dielectric material for semiconductor structure fabrication includes forming a trench in a material layer. The method also includes filling the trench with a porous dielectric material using a spin-on deposition process. The method also includes filling pores of the porous dielectric material with a metal-containing material using an atomic layer deposition (ALD) process.

公开(公告)号：US20190139887A1

公开(公告)日：2019-05-09

申请号：US16096272

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Richard E. SCHENKER ,  Jeffery D. BIELEFELD ,  Rami HOURANI ,  Manish CHANDHOK

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US20210225698A1

公开(公告)日：2021-07-22

申请号：US17218080

申请日：2021-03-30

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Richard E. SCHENKER ,  Jeffery D. BIELEFELD ,  Rami HOURANI ,  Manish CHANDHOK

IPC: H01L21/768 ,  H01L23/528

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US20190229264A1

公开(公告)日：2019-07-25

申请号：US16320010

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Roza KOTLYAR ,  Prashant MAJHI ,  Jeffery D. BIELEFELD

IPC: H01L45/00

Abstract: Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.

公开(公告)号：US20180226289A1

公开(公告)日：2018-08-09

申请号：US15745235

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Jeffery D. BIELEFELD ,  Manish CHANDHOK ,  Asad IQBAL ,  John D. BROOKS

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295

Abstract: A helmet layer is deposited on a plurality of conductive features on a first dielectric layer on a substrate. A second dielectric layer is deposited on a first portion of the helmet layer. An etch stop layer is deposited on a second portion the helmet layer.

公开(公告)号：US20190385897A1

公开(公告)日：2019-12-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Sudipto NASKAR ,  Stephanie A. BOJARSKI ,  Kevin LIN ,  Marie KRYSAK ,  Tristan A. TRONIC ,  Hui Jae YOO ,  Jeffery D. BIELEFELD ,  Jessica M. TORRES

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.