公开(公告)号：US20230130944A1

公开(公告)日：2023-04-27

申请号：US18089213

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20250149462A1

公开(公告)日：2025-05-08

申请号：US19016786

申请日：2025-01-10

Applicant: Intel Corporation

Inventor： John S. GUZEK

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07

Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (POP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.

公开(公告)号：US20240006331A1

公开(公告)日：2024-01-04

申请号：US18368929

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： John S. GUZEK

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/56 ,  H01L23/498 ,  H01L25/07 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L21/568 ,  H01L23/49816 ,  H01L25/07 ,  H01L21/56 ,  H01L25/065 ,  H01L23/48 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2225/06517 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L23/3128

Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.

公开(公告)号：US20230420400A1

公开(公告)日：2023-12-28

申请号：US18244689

申请日：2023-09-11

Applicant: Intel Corporation

Inventor： Pramod MALATKAR ,  Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN

IPC: H01L23/00 ,  H01L27/08 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L24/09 ,  H01L27/08 ,  H01L24/19 ,  H01L24/97 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552

Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

公开(公告)号：US20240421073A1

公开(公告)日：2024-12-19

申请号：US18818285

申请日：2024-08-28

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20230040850A1

公开(公告)日：2023-02-09

申请号：US17972340

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20220068861A1

公开(公告)日：2022-03-03

申请号：US17523787

申请日：2021-11-10

Applicant: Intel Corporation

Inventor： Pramod MALATKAR ,  Weng Hong TEH ,  John S. GUZEK ,  Robert L. SANKMAN

IPC: H01L23/00 ,  H01L27/08 ,  H01L23/48 ,  H01L23/538

Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

公开(公告)号：US20220336229A1

公开(公告)日：2022-10-20

申请号：US17850790

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Robert L. SANKMAN ,  John S. GUZEK

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H01L21/50 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

公开(公告)号：US20210134731A1

公开(公告)日：2021-05-06

申请号：US17149670

申请日：2021-01-14

Applicant: Intel Corporation

Inventor： John S. GUZEK

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/56 ,  H01L23/498 ,  H01L25/07 ,  H01L25/065 ,  H01L23/48

Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.

公开(公告)号：US20190006325A1

公开(公告)日：2019-01-03

申请号：US16127004

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： Weng Hong TEH ,  John S. GUZEK ,  Shan ZHONG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/12 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L23/13

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.