公开(公告)号：US10020931B2

公开(公告)日：2018-07-10

申请号：US13789241

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Mohamed A. Abdelmoneum ,  Nasser A. Kurd ,  Amr M. Lotfy ,  Mamdouh O. Abd El-Mejeed ,  Mohamed A. Abdelsalam

IPC: H03D3/24 ,  H04L7/033 ,  H03L7/099

CPC classification number: H04L7/0331 ,  H03L7/0995 ,  H04L7/033

Abstract: Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.

公开(公告)号：US09628094B2

公开(公告)日：2017-04-18

申请号：US14127963

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Amr M. Lotfy ,  Mohamed A. Abdelsalam ,  Mamdouh O. Abd El-Mejeed ,  Nasser A. Kurd ,  Mohamed A. Abdelmoneum ,  Mark Elzinga ,  Young Min Park ,  Jagannadha R. Rapeta ,  Surya Musunuri

IPC: H03L7/06 ,  H03L7/10 ,  G04F10/00 ,  H03L7/099 ,  H03L7/085

CPC classification number: H03L7/105 ,  G04F10/005 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/103 ,  H03L2207/06

Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.