公开(公告)号：US11949446B2

公开(公告)日：2024-04-02

申请号：US16912741

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Mark Elzinga ,  Martin Clara

IPC: H04L27/00 ,  H01Q1/24 ,  H01Q23/00 ,  H04B1/04 ,  H04B1/58

CPC classification number: H04B1/582 ,  H01Q1/246 ,  H01Q23/00 ,  H04B1/0475 ,  H04B2001/0433

Abstract: The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.

公开(公告)号：US11495382B2

公开(公告)日：2022-11-08

申请号：US16252618

申请日：2019-01-19

Applicant: Intel Corporation

Inventor： Mark Elzinga

IPC: H01F17/00 ,  H03L7/093 ,  H03L7/099 ,  H01F41/04 ,  H03B5/08

Abstract: Described is a high Q-factor inductor. The inductor is formed as a unit cell coil, which is copied twice for a dual-coil inductor and copied four times for a quad-coil inductor. For each copy of the unit cell coil, the coil is rotated a subsequent substantially 90 degrees or substantially −90 degrees. The rotation enables the terminals of the inductor to be routed equal-distant to a circuit that is placed in the line of symmetry between the two coils.

公开(公告)号：US10944411B1

公开(公告)日：2021-03-09

申请号：US16728601

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Mark Elzinga ,  Youngmin Park ,  Michael Bichan ,  Michael W. Altmann ,  Noam Familia ,  Vadim Levin ,  Dror Lazar

IPC: H03L7/10 ,  H03M3/00 ,  H03L7/099 ,  H03L7/18 ,  H03L7/187

Abstract: Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.

公开(公告)号：US20200234864A1

公开(公告)日：2020-07-23

申请号：US16252618

申请日：2019-01-19

Applicant: Intel Corporation

Inventor： Mark Elzinga

IPC: H01F17/00 ,  H03L7/093 ,  H03L7/099 ,  H03B5/08 ,  H01F41/04

Abstract: Described is a high Q-factor inductor. The inductor is formed as a unit cell coil, which is copied twice for a dual-coil inductor and copied four times for a quad-coil inductor. For each copy of the unit cell coil, the coil is rotated a subsequent substantially 90 degrees or substantially −90 degrees. The rotation enables the terminals of the inductor to be routed equal-distant to a circuit that is placed in the line of symmetry between the two coils.

公开(公告)号：US20170257106A1

公开(公告)日：2017-09-07

申请号：US15464039

申请日：2017-03-20

Applicant: INTEL CORPORATION

Inventor： Young Min Park ,  Mark Elzinga

IPC: H03M1/06 ,  G04F10/00

CPC classification number: H03M1/0626 ,  G04F10/005 ,  H03M1/0607

Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

公开(公告)号：US09628094B2

公开(公告)日：2017-04-18

申请号：US14127963

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Amr M. Lotfy ,  Mohamed A. Abdelsalam ,  Mamdouh O. Abd El-Mejeed ,  Nasser A. Kurd ,  Mohamed A. Abdelmoneum ,  Mark Elzinga ,  Young Min Park ,  Jagannadha R. Rapeta ,  Surya Musunuri

IPC: H03L7/06 ,  H03L7/10 ,  G04F10/00 ,  H03L7/099 ,  H03L7/085

CPC classification number: H03L7/105 ,  G04F10/005 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/103 ,  H03L2207/06

Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

公开(公告)号：US10581444B2

公开(公告)日：2020-03-03

申请号：US16057754

申请日：2018-08-07

Applicant: Intel Corporation

Inventor： Young Min Park ,  Mark Elzinga

IPC: H03M1/06 ,  G04F10/00

Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

公开(公告)号：US10075175B2

公开(公告)日：2018-09-11

申请号：US15464039

申请日：2017-03-20

Applicant: INTEL CORPORATION

Inventor： Young Min Park ,  Mark Elzinga

IPC: G04F10/00 ,  H03M1/06

CPC classification number: H03M1/0626 ,  G04F10/005 ,  H03M1/0607

Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.