公开(公告)号：US20190220054A1

公开(公告)日：2019-07-18

申请号：US16252471

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Surya Musunuri ,  Jagannadha R. Rapeta ,  Mark L. Elzinga ,  Young Min Park ,  Robert R. Fulton

IPC: G06F1/08 ,  G06F13/40 ,  H03L7/183 ,  G06F13/36

CPC classification number: G06F1/08 ,  G06F13/36 ,  G06F13/4068 ,  H03L7/183 ,  H03L2207/50

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

公开(公告)号：US10185349B2

公开(公告)日：2019-01-22

申请号：US14917928

申请日：2013-12-03

Applicant: Intel Corporation

Inventor： Surya Musunuri ,  Jagannadha R. Rapeta ,  Mark L. Elzinga ,  Young Min Park ,  Robert Fulton

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/183 ,  G06F13/36 ,  G06F13/40

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

公开(公告)号：US09628094B2

公开(公告)日：2017-04-18

申请号：US14127963

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Amr M. Lotfy ,  Mohamed A. Abdelsalam ,  Mamdouh O. Abd El-Mejeed ,  Nasser A. Kurd ,  Mohamed A. Abdelmoneum ,  Mark Elzinga ,  Young Min Park ,  Jagannadha R. Rapeta ,  Surya Musunuri

IPC: H03L7/06 ,  H03L7/10 ,  G04F10/00 ,  H03L7/099 ,  H03L7/085

CPC classification number: H03L7/105 ,  G04F10/005 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/103 ,  H03L2207/06

Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

公开(公告)号：US10712768B2

公开(公告)日：2020-07-14

申请号：US16252471

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Surya Musunuri ,  Jagannadha R. Rapeta ,  Mark L. Elzinga ,  Young Min Park ,  Robert R. Fulton

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/183 ,  G06F13/36 ,  G06F13/40

Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.

公开(公告)号：US10581444B2

公开(公告)日：2020-03-03

申请号：US16057754

申请日：2018-08-07

Applicant: Intel Corporation

Inventor： Young Min Park ,  Mark Elzinga

IPC: H03M1/06 ,  G04F10/00

Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

公开(公告)号：US10075175B2

公开(公告)日：2018-09-11

申请号：US15464039

申请日：2017-03-20

Applicant: INTEL CORPORATION

Inventor： Young Min Park ,  Mark Elzinga

IPC: G04F10/00 ,  H03M1/06

CPC classification number: H03M1/0626 ,  G04F10/005 ,  H03M1/0607

Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

公开(公告)号：US20170257106A1

公开(公告)日：2017-09-07

申请号：US15464039

申请日：2017-03-20

Applicant: INTEL CORPORATION

Inventor： Young Min Park ,  Mark Elzinga

IPC: H03M1/06 ,  G04F10/00

CPC classification number: H03M1/0626 ,  G04F10/005 ,  H03M1/0607

Abstract: Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

公开(公告)号：US11144088B2

公开(公告)日：2021-10-12

申请号：US16430170

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Jagannadha Rao V. V. V. Rapeta ,  Mikal Hunsaker ,  Ronald Swartz ,  Robert Fulton ,  L. Mark Elzinga ,  Young Min Park ,  David R. Mulvihill

IPC: G06F1/12 ,  G06F13/42

Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.

公开(公告)号：US20190332139A1

公开(公告)日：2019-10-31

申请号：US16430170

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Jagannadha Rao V. V. V. Rapeta ,  Mikal Hunsaker ,  Ronald Swartz ,  Robert Fulton ,  L. Mark Elzinga ,  Young Min Park ,  David R. Mulvihill

IPC: G06F1/12 ,  G06F13/42

Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.