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    MEMORY THIN PROVISIONING USING MEMORY POOLS
    2.
    发明申请
    MEMORY THIN PROVISIONING USING MEMORY POOLS 有权

    公开(公告)号：US20210200667A1

    公开(公告)日：2021-07-01

    申请号：US16727595

    申请日：2019-12-26

    Applicant: Intel Corporation

    Inventor： Debra BERNSTEIN ,  Hugh WILKINSON ,  Douglas CARRIGAN ,  Bassam N. COURY ,  Matthew J. ADILETTA ,  Durgesh SRIVASTAVA ,  Lidia WARNES ,  William WHEELER ,  Michael F. FALLON

    IPC: G06F12/02 ,  G06F3/06

    Abstract: Examples described herein relate to memory thin provisioning in a memory pool of one or more dual in-line memory modules or memory devices. At any instance, any central processing unit (CPU) can request and receive a full virtual allocation of memory in an amount that exceeds the physical memory attached to the CPU (near memory). A remote pool of additional memory can be dynamically utilized to fill the gap between allocated memory and near memory. This remote pool is shared between multiple CPUs, with dynamic assignment and address re-mapping provided for the remote pool. To improve performance, the near memory can be operated as a cache of the pool memory. Inclusive or exclusive content storage configurations can be applied. An inclusive cache configuration can include an entry in a near memory cache also being stored in a memory pool whereas an exclusive cache configuration can provide an entry in either a near memory cache or in a memory pool but not both. Near memory cache management includes current data location tracking, access counting and other caching heuristics, eviction of data from near memory cache to pool memory and movement of data from pool memory to memory cache.

    RESERVATION OF MEMORY IN MULTIPLE TIERS OF MEMORY
    3.
    发明公开
    RESERVATION OF MEMORY IN MULTIPLE TIERS OF MEMORY 审中-公开

    公开(公告)号：US20230305720A1

    公开(公告)日：2023-09-28

    申请号：US18084258

    申请日：2022-12-19

    Applicant: Intel Corporation

    Inventor： Slawomir PUTYRSKI ,  Matthew J. ADILETTA

    IPC: G06F3/06

    CPC classification number: G06F3/0631 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0611

    Abstract: Examples described herein relate to a memory controller, when connected to at least one memory device in a multi-tiered memory system comprising a near memory and far memory, is to allocate a region of the near memory to a requester based on receipt of a request. In some examples, the memory controller includes circuitry to transmit at least one memory read command and address information to the multi-tiered memory system to read data from the multi-tiered memory system and circuitry to transmit at least one memory write command and address information to the multi-tiered memory system to write data to the multi-tiered memory system, wherein the near memory comprises at least one memory connected to the memory controller via a memory interface and the far memory comprises at least one memory connected to the memory controller via a network.

    MICROSERVICE DEPLOYMENTS USING ACCELERATORS
    6.
    发明申请
    MICROSERVICE DEPLOYMENTS USING ACCELERATORS 有权

    公开(公告)号：US20230100935A1

    公开(公告)日：2023-03-30

    申请号：US18075262

    申请日：2022-12-05

    Applicant: Intel Corporation

    Inventor： Kelley MULLICK ,  Mrittika GANGULI ,  Brian P. JOHNSON ,  Matthew J. ADILETTA

    IPC: G06F9/50 ,  G06F9/54

    Abstract: Examples described herein relate to circuitry to perform load balancing; at least one memory; and at least one processor. In some examples, at least one processor is to execute instructions stored in the at least one memory that cause the at least one processor to: execute a communication proxy that is to allocate packet data to the circuitry to perform load balancing to allocate workloads among cores and allocate received and transmitted remote procedure calls to at least one queue in circuitry to queue one or more packets.

    CROSS DRAM DIMM SUB-CHANNEL PAIRING
    10.
    发明公开
    CROSS DRAM DIMM SUB-CHANNEL PAIRING 审中-公开

    公开(公告)号：US20230215493A1

    公开(公告)日：2023-07-06

    申请号：US18120907

    申请日：2023-03-13

    Applicant: Intel Corporation

    Inventor： Duane E. GALBI ,  Matthew J. ADILETTA ,  Mohammad M. RASHID ,  Todd HINCK ,  Vijaya K. BODDU

    IPC: G11C11/4093 ,  G11C11/4076 ,  G11C5/06 ,  G11C11/4096

    CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C5/06 ,  G11C11/4096

    Abstract: Methods and apparatus for Cross DRAM DIMM sub-channel pairing. Memory channels on a memory controller or System on a Chip (SoC) are segmented into two subchannels, each including Command and Address (C/A) signals, DQ (data) lines. Under different solutions the two subchannels may share a command-bus clock or use separate command-bus clocks. Some approaches use subchannels from different memory channels to provide the C/A and DQ lines for two subchannels to a given DIMM. One solution implements an additional command-bus clock on the DIMM connector repurposing existing MCR pins to provide command-bus clock signals to a Registered Clock Driver (RCD) to allow the subchannels to be fully independent. Another solution is the pair every other DRAM controller to the same command-bus clock. Other solutions employ Skip-1, Skip-2, and Skip-3 configurations under which the clocks for the DDR-IO circuitry are not logically co-located with the subchannel IO circuitry.

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