公开(公告)号：US09921630B2

公开(公告)日：2018-03-20

申请号：US14948174

申请日：2015-11-20

Applicant: Intel Corporation

Inventor： Gururaj K. Shamanna ,  Stefan Rusu ,  Phani Kumar Kandula ,  Sankalan Prasad ,  Mandar R. Ranade ,  Narayanan Natarajan ,  Tessil Thomas

IPC: G06F1/32 ,  G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

公开(公告)号：US09696350B2

公开(公告)日：2017-07-04

申请号：US13907802

申请日：2013-05-31

Applicant: INTEL CORPORATION

Inventor： Edward A. Burton ,  Gerhard Schrom ,  Michael W. Rogers ,  Alexander Lyakhov ,  Ravi Sankar Vunnam ,  Jonathan P. Douglas ,  Fabrice Paillet ,  J. Keith Hodgson ,  William Dawson Kesling ,  Chiu Keung Tang ,  Narayanan Raghuraman ,  Narayanan Natarajan ,  Samie Samaan ,  George Geannopoulos

IPC: H02M3/157 ,  G01R19/00 ,  H03L5/00 ,  H03M1/66 ,  G06T3/40 ,  H02M3/156 ,  H02M1/088 ,  H02M3/158 ,  H03M1/68 ,  H02M1/00

CPC classification number: G01R19/0092 ,  G06T3/40 ,  H02M1/088 ,  H02M3/156 ,  H02M3/157 ,  H02M3/158 ,  H02M2001/0009 ,  H02M2003/1566 ,  H03L5/00 ,  H03M1/66 ,  H03M1/685

Abstract: Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

公开(公告)号：US10404152B2

公开(公告)日：2019-09-03

申请号：US15721314

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Srikrishnan Venkataraman ,  Sreedhar Narayanaswamy ,  Jonathan P. Douglas ,  Chih-Chung Jonathan Wei ,  Ankush Varma ,  Narayanan Natarajan

IPC: H02M1/00 ,  G06F1/26 ,  H03L7/099

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

公开(公告)号：US20190103801A1

公开(公告)日：2019-04-04

申请号：US15721314

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Srikrishnan Venkataraman ,  Sreedhar Narayanaswamy ,  Jonathan P. Douglas ,  Chih-Chung Jonathan Wei ,  Ankush Varma ,  Narayanan Natarajan

IPC: H02M1/00 ,  G06F1/26

CPC classification number: H02M1/00 ,  G06F1/26 ,  H02M3/158 ,  H02M3/33561 ,  H02M2001/0009 ,  H02M2001/0012 ,  H02M2001/008 ,  H03L7/099

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

公开(公告)号：US09733282B2

公开(公告)日：2017-08-15

申请号：US14543346

申请日：2014-11-17

Applicant: INTEL CORPORATION

Inventor： Gerhard Schrom ,  J. Keith Hodgson ,  Alexander Lyakhov ,  Chiu Keung Tang ,  Narayanan Raghuraman ,  Narayanan Natarajan

IPC: H03M1/66 ,  G01R19/00 ,  H02M3/157 ,  H03L5/00 ,  G06T3/40 ,  H02M3/156 ,  H02M1/088 ,  H02M3/158 ,  H03M1/68 ,  H02M1/00

CPC classification number: G01R19/0092 ,  G06T3/40 ,  H02M1/088 ,  H02M3/156 ,  H02M3/157 ,  H02M3/158 ,  H02M2001/0009 ,  H02M2003/1566 ,  H03L5/00 ,  H03M1/66 ,  H03M1/685

Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. are provided here. An apparatus is provided which comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

公开(公告)号：US09207750B2

公开(公告)日：2015-12-08

申请号：US13715624

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Gururaj K. Shamanna ,  Stefan Rusu ,  Phani Kumar Kandula ,  Sankalan Prasad ,  Mandar R. Ranade ,  Narayanan Natarajan ,  Tessil Thomas

IPC: G06F1/32

CPC classification number: G06F1/28 ,  G05F1/625 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Abstract translation: 描述了一种处理器，包括：多个晶体管，其可操作以提供动态可调节的晶体管尺寸，所述多个晶体管的一端耦合到第一电源并在另一端耦合到第二电源; 耦合到所述第二电源的电路，所述第二电源向所述电路提供电力; 以及功率控制单元（PCU），用于监测第一电源的电平，并且动态地调整多个晶体管的晶体管尺寸，使得调节第二电源以保持电路的可操作性。

公开(公告)号：US11193961B2

公开(公告)日：2021-12-07

申请号：US16866347

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Gerhard Schrom ,  J. Keith Hodgson ,  Alexander Lyakhov ,  Chiu Keung Tang ,  Narayanan Raghuraman ,  Narayanan Natarajan

IPC: H03M1/66 ,  G01R19/00 ,  H02M3/157 ,  H02M3/156 ,  H03L5/00 ,  G06T3/40 ,  H02M1/088 ,  H02M3/158 ,  H03M1/68 ,  H02M1/00

Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, a plurality of inductors is coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge

公开(公告)号：US20220375898A1

公开(公告)日：2022-11-24

申请号：US17323094

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Vishram Shriram Pandit ,  Narayanan Natarajan ,  Jayanth M. Kalyan ,  Khondker Z. Ahmed ,  Jonathan P. Douglas ,  Gururaj K. Shamanna ,  Chin Lee Kuan

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48

Abstract: An Integrated Circuit (IC) package is provided, comprising a first IC die having a first capacitor and a logic circuit, and a second IC die having a second capacitor. The first IC die and the second IC die may be stacked within the IC package one on top of another and electrically coupled with die-to-die interconnects. The logic circuit is electrically coupled in a power delivery network to the first capacitor and the second capacitor. The first IC die and the second IC die include respective back-end-of-line portions in which the first capacitor and the second capacitor, which may comprise metal-insulator-metal capacitors in some embodiments are situated. In some embodiments, the second capacitor is situated in a shadow of the logic circuit. In various embodiments, the first IC die and the second IC die comprise any suitable pair in a plurality of stacked IC dies within an IC package.

公开(公告)号：US10184961B2

公开(公告)日：2019-01-22

申请号：US15276697

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Gerhard Schrom ,  J. Keith Hodgson ,  Alexander Lyakhov ,  Chiu Keung Tang ,  Narayanan Raghuraman ,  Narayanan Natarajan

IPC: H03M1/66 ,  G01R19/00 ,  H02M3/157 ,  H03L5/00 ,  G06T3/40 ,  H02M3/156 ,  H02M1/088 ,  H02M3/158 ,  H03M1/68 ,  H02M1/00

Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

公开(公告)号：US20160077567A1

公开(公告)日：2016-03-17

申请号：US14948174

申请日：2015-11-20

Applicant: Intel Corporation

Inventor： Gururaj K. Shamanna ,  Stefan Rusu ,  Phani Kumar Kandula ,  Sankalan Prasad ,  Mandar R. Ranade ,  Narayanan Natarajan ,  Tessil Thomas

IPC: G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Abstract translation: 描述了一种处理器，包括：多个晶体管，其可操作以提供动态可调节的晶体管尺寸，所述多个晶体管的一端耦合到第一电源并在另一端耦合到第二电源; 耦合到所述第二电源的电路，所述第二电源向所述电路提供电力; 以及功率控制单元（PCU），用于监测第一电源的电平，并且动态地调整多个晶体管的晶体管尺寸，使得调节第二电源以保持电路的可操作性。