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公开(公告)号：US20230208437A1
公开(公告)日：2023-06-29
申请号：US17561246
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Sami Hyvonen , Fabrice Paillet , James Keith Hodgson , Anand Ramasundar , Cary Renzema , George Matthew , Sergio Carlo Rodriguez , Po-Cheng Chen , Sandeep Chilka , Bharadwaj Soundararajan
Abstract: A digitally selectable power gate with thermometer-encoded upper bits may provide solutions for problems digital power gate-based regulators. These solutions may include the use of a fully binary power gate, either in structure or by local decoding of binary control signal to an addressable row-based power gate. This provides improved performance over a row-based code rotation, which is intended to avoid instantaneous overheating of power gate devices but may not mitigate aging effects. Another solution includes ganging a primary DLVR and one or more secondaries. The primary DLVR may include a voltage sense and active controller, which may forward its PG code to secondary instances. Therm and current sensor rotation may be performed locally at the secondaries and a current monitor data may be rolled up from all ganged DLVRs.
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公开(公告)号：US20220065901A1
公开(公告)日：2022-03-03
申请号：US17006715
申请日：2020-08-28
Applicant: Intel Corporation
Inventor： Nachiket Desai , Harish Krishnamurthy , Suhwan Kim , Fabrice Paillet
Abstract: A current sensing topology uses an amplifier with capacitively coupled inputs in feedback to sense the input offset of the amplifier, which can be compensated for during measurement. The amplifier with capacitively coupled inputs in feedback is used to: operate the amplifier in a region where the input common-mode specifications are relaxed, so that the feedback loop gain and/or bandwidth is higher; operate the sensor from the converter input voltage by employing high-PSRR (power supply rejection ratio) regulators to create a local, clean supply voltage, causing less disruption to the power grid in the switch area; sample the difference between the input voltage and the controller supply, and recreate that between the drain voltages of the power and replica switches; and compensate for power delivery network related (PDN-related) changes in the input voltage during current sensing.
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公开(公告)号：US20170117795A1
公开(公告)日：2017-04-27
申请号：US15402021
申请日：2017-01-09
Applicant: INTEL CORPORATION
Inventor： Gerhard Schrom , Naravanan Raghuraman , Fabrice Paillet
CPC classification number: H02M1/14 , G06F1/26 , H02M2003/1586 , H03H7/325 , H03H11/265 , H03K3/0315 , H03K4/06 , H03K5/133 , H03K5/134 , H03K7/08 , H03K2005/00019 , H03K2005/00195 , H03L7/00
Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.
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公开(公告)号：US20160239036A1
公开(公告)日：2016-08-18
申请号：US14621261
申请日：2015-02-12
Applicant: Intel Corporation
Inventor： Fabrice Paillet , Gerhard Schrom , Anant Deval , Rajan Vijayaraghavan
CPC classification number: G05F3/08 , G05F1/46 , G06F1/26 , H02M3/1584 , H02M2001/0045 , H02M2001/007 , H02M2001/008
Abstract: The present disclosure provides a power delivery scheme to provide a parallel regulation feature for integrated voltage regulators (IVRs).
Abstract translation: 本公开提供了为集成稳压器（IVR）提供并行调节特征的功率传递方案。
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公开(公告)号：US20230205244A1
公开(公告)日：2023-06-29
申请号：US17561109
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Anand Ramasundar , Cary Renzema , Fabrice Paillet , James Keith Hodgson , Po-Cheng Chen , Sergio Carlo Rodriguez , Harish K. Krishnamurthy , Jason Muhlestein
Abstract: An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.
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Patent Agency Ranking
公开(公告)号：US20230168705A1
公开(公告)日：2023-06-01
申请号：US17540046
申请日：2021-12-01
Applicant: Intel Corporation
Inventor： Sergio Carlo Rodriguez , Cary D, Renzema , Amit K. Jain , Po-Cheng Chen , Fabrice Paillet , Anand Ramasundar , James Keith Hodgson
IPC: G05F1/577
CPC classification number: G05F1/577
Abstract: Embodiments herein relate to a feedback loop in a digital voltage regulator for controlling an output voltage. To avoid instability at light current loads, a gain of the loop is reduced as a power gate code indicates a reduced number of branches in set of current sources are enabled. In an example implementation, the code is classified into one range of a number of ranges, and the gain is set based on the one range. The gain can decrease each time the code enters a lower range, as indicated by the code crossing a threshold or predetermined value. For example, the gain can decrease by half each time the code enters a lower range.
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公开(公告)号：US11323026B2
公开(公告)日：2022-05-03
申请号：US16563495
申请日：2019-09-06
Applicant: Intel Corporation
Inventor： Takao Oshita , Fabrice Paillet , Rinkle Jain , Jad Rizk , Danny Bronstein , Ahmad Arnaot
IPC: H02M3/07 , H02M1/00 , G06F1/3234 , H03K5/24
Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
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公开(公告)号：US11757357B2
公开(公告)日：2023-09-12
申请号：US17714969
申请日：2022-04-06
Applicant: Intel Corporation
Inventor： Takao Oshita , Fabrice Paillet , Rinkle Jain , Jad Rizk , Danny Bronstein , Ahmad Arnaot
IPC: H02M3/07 , G06F1/3234 , H03K5/24 , H02M1/00
CPC classification number: H02M3/073 , G06F1/3234 , H02M1/00 , H02M3/07 , H02M3/072 , H03K5/249 , H02M1/0012 , H02M1/0045 , H02M3/077
Abstract: An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).
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9.发明授权公开(公告)号：US11429173B2
公开(公告)日：2022-08-30
申请号：US16230440
申请日：2018-12-21
Applicant: Intel Corporation
Inventor： Chee Lim Nge , Amit Jain , Anant Deval , Nimrod Angel , Fabrice Paillet , Michael Zelikson , Sergio Carlo Rodriguez
IPC: G06F1/26 , G06F1/32 , G06F1/3206 , H02M3/158 , H02M1/08 , G06F1/20 , G06F1/3296 , H02M1/32 , G06F1/324 , H02M1/00 , H02M3/156
Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.
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公开(公告)号：US20220069703A1
公开(公告)日：2022-03-03
申请号：US17009661
申请日：2020-09-01
Applicant: Intel Corporation
Inventor： Harish Krishnamurthy , Sheldon Weng , Nachiket Desai , Suhwan Kim , Fabrice Paillet
Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.
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