公开(公告)号：US09733282B2

公开(公告)日：2017-08-15

申请号：US14543346

申请日：2014-11-17

Applicant: INTEL CORPORATION

Inventor： Gerhard Schrom ,  J. Keith Hodgson ,  Alexander Lyakhov ,  Chiu Keung Tang ,  Narayanan Raghuraman ,  Narayanan Natarajan

IPC: H03M1/66 ,  G01R19/00 ,  H02M3/157 ,  H03L5/00 ,  G06T3/40 ,  H02M3/156 ,  H02M1/088 ,  H02M3/158 ,  H03M1/68 ,  H02M1/00

CPC classification number: G01R19/0092 ,  G06T3/40 ,  H02M1/088 ,  H02M3/156 ,  H02M3/157 ,  H02M3/158 ,  H02M2001/0009 ,  H02M2003/1566 ,  H03L5/00 ,  H03M1/66 ,  H03M1/685

Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. are provided here. An apparatus is provided which comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

公开(公告)号：US20150333628A1

公开(公告)日：2015-11-19

申请号：US14810385

申请日：2015-07-27

Applicant: Intel Corporation

Inventor： Gerhard Schrom ,  Mark S. Milshtein ,  Alexander Lyakhov

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/08 ,  H02M3/1588 ,  H02M3/338 ,  Y02B70/1466

Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.

Abstract translation: 描述了一种装置，其包括：耦合到输出节点的低侧开关，用于提供稳压电压; 以及第一驱动器，其可操作以在所述输出节点上升到高于第一晶体管阈值电压时使所述低侧开关断开。 还描述了一种电压调节器，其包括：产生脉冲宽度调制（PWM）信号的信号发生器; 具有耦合到输出节点的低侧开关的桥，用于根据所述PWM信号提供稳压电源; 第一驱动器，其可操作以在所述输出节点上升到高于第一晶体管阈值电压时使所述低侧开关断开; 以及桥控制器，用于向第一驱动器提供控制信号。 电压调节器可以在没有二极管钳位的情况下工作，并且其操作是自定时的。 电压调节器还提供了过程变化的公差。

公开(公告)号：US11755048B2

公开(公告)日：2023-09-12

申请号：US17220802

申请日：2021-04-01

Applicant: Intel Corporation

Inventor： Sergio Carlo Rodriguez ,  Alexander Lyakhov ,  Gerhard Schrom ,  Keith Hodgson ,  Sarath S. Makala ,  Sidhanto Roy

IPC: H02M3/157 ,  G05F1/652 ,  G05F1/44 ,  H03M1/66 ,  H02M1/00

CPC classification number: G05F1/652 ,  G05F1/44 ,  H02M3/157 ,  H02M1/0025 ,  H03M1/66

Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.

公开(公告)号：US11193961B2

公开(公告)日：2021-12-07

申请号：US16866347

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Gerhard Schrom ,  J. Keith Hodgson ,  Alexander Lyakhov ,  Chiu Keung Tang ,  Narayanan Raghuraman ,  Narayanan Natarajan

IPC: H03M1/66 ,  G01R19/00 ,  H02M3/157 ,  H02M3/156 ,  H03L5/00 ,  G06T3/40 ,  H02M1/088 ,  H02M3/158 ,  H03M1/68 ,  H02M1/00

Abstract: Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, a plurality of inductors is coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge

公开(公告)号：US20210223811A1

公开(公告)日：2021-07-22

申请号：US17220802

申请日：2021-04-01

Applicant: Intel Corporation

Inventor： Sergio Carlo Rodriguez ,  Alexander Lyakhov ,  Gerhard Schrom ,  Keith Hodgson ,  Sarath S. Makala ,  Sidhanto Roy

IPC: G05F1/652 ,  H02M3/157 ,  G05F1/44

Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.

公开(公告)号：US20200004286A1

公开(公告)日：2020-01-02

申请号：US16566368

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Gerhard Schrom ,  Vaughn J. Grossnickle ,  Nasser A. Kurd

IPC: G05F1/625 ,  H03L7/093 ,  H03K5/24 ,  G01R19/165

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

公开(公告)号：US10367409B2

公开(公告)日：2019-07-30

申请号：US15402021

申请日：2017-01-09

Applicant: INTEL CORPORATION

Inventor： Gerhard Schrom ,  Narayanan Raghuraman ,  Fabrice Paillet

IPC: H02M1/14 ,  H03K4/06 ,  G06F1/26 ,  H03L7/00 ,  H03K3/03 ,  H03K7/08 ,  H03K5/134 ,  H02M3/158 ,  H03H7/32 ,  H03H11/26 ,  H03K5/133 ,  H03K5/00

Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

公开(公告)号：US10134727B2

公开(公告)日：2018-11-20

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L29/00 ,  H01L27/06 ,  H01L29/94 ,  H01L29/04 ,  H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8252 ,  H01L21/8258

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

公开(公告)号：US20180284828A1

公开(公告)日：2018-10-04

申请号：US15478457

申请日：2017-04-04

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Gerhard Schrom ,  Vaughn J. Grossnickle ,  Nasser A. Kurd

IPC: G05F1/625 ,  H03L7/093 ,  H03K5/24 ,  G01R19/165

CPC classification number: G05F1/625 ,  G01R19/16552 ,  H03K5/24 ,  H03L7/06

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.

公开(公告)号：US20160365341A1

公开(公告)日：2016-12-15

申请号：US14738799

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/20 ,  H01L29/10 ,  H01L29/205 ,  H01L29/94 ,  H01L29/778

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/7787 ,  H01L29/94 ,  H01L29/945

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract translation: 集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。 可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。 在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术 。 在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。 在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。