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1.发明授权公开(公告)号：US10261792B2
公开(公告)日：2019-04-16
申请号：US15408632
申请日：2017-01-18
Applicant: Intel Corporation
Inventor： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
IPC: G06F9/30 , G06F11/34 , G06F12/0875
Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
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公开(公告)号：US20170235580A1
公开(公告)日：2017-08-17
申请号：US15586930
申请日：2017-05-04
Applicant: Intel Corporation
Inventor： Laura A. Knauth , Ravi Rajwar , Peggy J. Irelan , Konrad K. Lai , Martin G. Dixon
IPC: G06F9/38 , G06F9/46 , G06F12/084 , G06F13/42 , G06F9/30 , G06F12/0875
CPC classification number: G06F9/3861 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F9/528 , G06F11/1407 , G06F11/1469 , G06F11/3048 , G06F11/3051 , G06F11/348 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F13/1673 , G06F13/4282 , G06F15/80 , G06F2201/84 , G06F2201/86 , G06F2201/88 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/62 , G06F2213/0026
Abstract: An example system for speculative execution event counter checkpointing and restoring may include a plurality of processors, a first interconnect to couple two or more of the plurality of processors, a second interconnect to couple one or more of the plurality of processors to one or more other system components, and a system memory coupled to one or more of the processors. At least one processor of the plurality of processors may include: a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores; and event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters; one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The processor may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The processor may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The processor may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.
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公开(公告)号：US20170235638A1
公开(公告)日：2017-08-17
申请号：US15586898
申请日：2017-05-04
Applicant: Intel Corporation
Inventor： Laura A. Knauth , Ravi Rajwar , Peggy J. Irelan , Konrad K. Lai , Martin G. Dixon
IPC: G06F11/14 , G06F13/42 , G06F13/16 , G06F11/34 , G06F9/30 , G06F9/52 , G06F12/084 , G06F12/0862 , G06F11/30
CPC classification number: G06F9/3861 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F9/528 , G06F11/1407 , G06F11/1469 , G06F11/3048 , G06F11/3051 , G06F11/348 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F13/1673 , G06F13/4282 , G06F15/80 , G06F2201/84 , G06F2201/86 , G06F2201/88 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/62 , G06F2213/0026
Abstract: An example system for speculative execution event counter checkpointing and restoring may include a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores. The system may further include a memory controller to couple the symmetric cores to a system memory and a data communication interface to couple one or more of the cores to input/output devices. The system may further include event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters and one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The system may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The system may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The system may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.
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公开(公告)号：US20170235579A1
公开(公告)日：2017-08-17
申请号：US15586636
申请日：2017-05-04
Applicant: Intel Corporation
Inventor： Laura A. Knauth , Ravi Rajwar , Peggy J. Irelan , Konrad K. Lai , Martin G. Dixon
IPC: G06F9/38 , G06F9/46 , G06F12/0875 , G06F12/084 , G06F15/80 , G06F9/30
CPC classification number: G06F9/3861 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F9/528 , G06F11/1407 , G06F11/1469 , G06F11/3048 , G06F11/3051 , G06F11/348 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F13/1673 , G06F13/4282 , G06F15/80 , G06F2201/84 , G06F2201/86 , G06F2201/88 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/62 , G06F2213/0026
Abstract: An example processor for speculative execution event counter checkpointing and restoring may include a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores. The processor may further include event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters and one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The processor may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The processor may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The processor may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.
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公开(公告)号：US10540193B2
公开(公告)日：2020-01-21
申请号：US15590781
申请日：2017-05-09
Applicant: INTEL CORPORATION
Inventor： Mingqiu Sun , Noah Zentzis , Vincent J. Zimmer , Peggy J. Irelan , Timothy E. Abels , Gopinatth Selvaraje , Rajesh Poornachandran
Abstract: A microservice infrastructure that securely maintains the currency of computing platform microservices implemented within a process virtual machine is provided. The computing platform microservices maintained by the infrastructure may include protected methods that provide and control access to components of the underlying computing environment. These components may include, for example, storage devices, peripherals, and network interfaces. By providing a software-defined microservice layer between these hardware components and workflows that specify high-level application logic, the embodiments disclosed herein have enhanced flexibility and scalability when compared to conventional technology.
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Patent Agency Ranking
公开(公告)号：US09971603B2
公开(公告)日：2018-05-15
申请号：US15438679
申请日：2017-02-21
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Peggy J. Irelan , Ofer Levy , Emile Ziedan , Grant G. Zhou
CPC classification number: G06F9/3861 , G06F9/3857 , G06F11/3466 , G06F11/3476 , G06F2201/86 , G06F2201/88
Abstract: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.
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7.发明申请公开(公告)号：US20170132004A1
公开(公告)日：2017-05-11
申请号：US15408632
申请日：2017-01-18
Applicant: Intel Corporation
Inventor： Michael W. Chynoweth , Peggy J. Irelan , Matthew C. Merten , Seung-Woo Kim , Laura A. Knauth , Stanislav Bratanov
IPC: G06F9/30 , G06F12/0875
CPC classification number: G06F9/30058 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/3016 , G06F11/3409 , G06F11/3476 , G06F11/348 , G06F12/0875
Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.
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公开(公告)号：US20180329729A1
公开(公告)日：2018-11-15
申请号：US15590781
申请日：2017-05-09
Applicant: INTEL CORPORATION
Inventor： Mingqiu Sun , Noah Zentzis , Vincent J. Zimmer , Peggy J. Irelan , Timothy E. Abels , Gopinatth Selvaraje , Rajesh Poornachandran
Abstract: A microservice infrastructure that securely maintains the currency of computing platform microservices implemented within a process virtual machine is provided. The computing platform microservices maintained by the infrastructure may include protected methods that provide and control access to components of the underlying computing environment. These components may include, for example, storage devices, peripherals, and network interfaces. By providing a software-defined microservice layer between these hardware components and workflows that specify high-level application logic, the embodiments disclosed herein have enhanced flexibility and scalability when compared to conventional technology.
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公开(公告)号：US20250036477A1
公开(公告)日：2025-01-30
申请号：US18913807
申请日：2024-10-11
Applicant: Intel Corporation
Inventor： Katalin Bartfai-Walcott , Peggy J. Irelan , Hassnaa Moustafa
Abstract: A compute system that includes an Internet of things (IoT) device is provided. The IoT device includes a common services interface (CSI) to create a self-managing network of devices with other nodes comprising the CSI.
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公开(公告)号：US11281499B2
公开(公告)日：2022-03-22
申请号：US16478593
申请日：2017-06-27
Applicant: INTEL CORPORATION
Inventor： Katalin Bartfai-Walcott , Peggy J. Irelan , Hassnaa Moustafa
Abstract: A compute system that includes an Internet of things (IoT) device is provided. The IoT device includes a common services interface (CSI) to create a self-managing network of devices with other nodes comprising the CSI.
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