公开(公告)号：US20170207185A1

公开(公告)日：2017-07-20

申请号：US15475793

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM A. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: H01L23/00 ,  H01L21/306 ,  G03F7/16 ,  H01L21/308 ,  G03F7/00 ,  G03F7/40

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20170139318A1

公开(公告)日：2017-05-18

申请号：US15419147

申请日：2017-01-30

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM M. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: G03F1/36 ,  G03F7/20 ,  G03F1/50 ,  H01L21/027 ,  H01L21/308

CPC classification number: H01L24/09 ,  G03F1/50 ,  G03F1/70 ,  G03F7/0035 ,  G03F7/16 ,  G03F7/40 ,  G03F7/70741 ,  H01L21/02345 ,  H01L21/0273 ,  H01L21/2633 ,  H01L21/30604 ,  H01L21/3086 ,  H01L27/0207 ,  H01L2224/0801 ,  H01L2224/08053 ,  H01L2224/0912 ,  H01L2924/14

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20200091101A1

公开(公告)日：2020-03-19

申请号：US16692589

申请日：2019-11-22

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM A. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: H01L23/00 ,  G03F1/36 ,  H01L21/027 ,  G03F1/70 ,  G03F7/00 ,  G03F7/40 ,  G03F7/20 ,  H01L21/02 ,  H01L21/263 ,  H01L27/02 ,  G03F1/50 ,  G03F7/16 ,  H01L21/306 ,  H01L21/308

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20160190009A1

公开(公告)日：2016-06-30

申请号：US14911991

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： CHARLES H. WALLACE ,  PAUL A. NYHUS ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76883 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.

Abstract translation: 描述了用于后端（BEOL）互连的上一层自对准通孔和插图图案。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的第一层。 互连结构的第一层包括在第一方向上交替的金属线和介质线的光栅。 互连结构的第二层设置在第一层上。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的光栅。 第二层的光栅的每个金属线设置在由互连结构的第一层的交替金属线和介电线对应的第一介电材料和第二介电材料的交替不同区域组成的凹陷介质线上。