公开(公告)号：US20190237404A1

公开(公告)日：2019-08-01

申请号：US16382414

申请日：2019-04-12

Applicant: INTEL CORPORATION

Inventor： BERNHARD SELL ,  OLEG GOLONZKA

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L23/528 ,  H01L27/088 ,  H01L21/28 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L23/522 ,  H01L23/485

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20180315710A1

公开(公告)日：2018-11-01

申请号：US15925151

申请日：2018-03-19

Applicant: INTEL CORPORATION

Inventor： BERNHARD SELL ,  OLEG GOLONZKA

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L23/528 ,  H01L27/088 ,  H01L21/28 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L23/522

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20170207185A1

公开(公告)日：2017-07-20

申请号：US15475793

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM A. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: H01L23/00 ,  H01L21/306 ,  G03F7/16 ,  H01L21/308 ,  G03F7/00 ,  G03F7/40

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20170141039A1

公开(公告)日：2017-05-18

申请号：US15419141

申请日：2017-01-30

Applicant: INTEL CORPORATION

Inventor： BERNHARD SELL ,  OLEG GOLONZKA

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768 ,  H01L27/088 ,  H01L29/417 ,  H01L21/28 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20190081233A1

公开(公告)日：2019-03-14

申请号：US16073687

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： KEVIN J. LEE ,  OLEG GOLONZKA ,  TAHIR GHANI ,  RUTH A. BRAIN ,  YIH WANG

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/14 ,  H01L43/08 ,  H01L43/10

Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

公开(公告)号：US20170139318A1

公开(公告)日：2017-05-18

申请号：US15419147

申请日：2017-01-30

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM M. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: G03F1/36 ,  G03F7/20 ,  G03F1/50 ,  H01L21/027 ,  H01L21/308

CPC classification number: H01L24/09 ,  G03F1/50 ,  G03F1/70 ,  G03F7/0035 ,  G03F7/16 ,  G03F7/40 ,  G03F7/70741 ,  H01L21/02345 ,  H01L21/0273 ,  H01L21/2633 ,  H01L21/30604 ,  H01L21/3086 ,  H01L27/0207 ,  H01L2224/0801 ,  H01L2224/08053 ,  H01L2224/0912 ,  H01L2924/14

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20200091101A1

公开(公告)日：2020-03-19

申请号：US16692589

申请日：2019-11-22

Applicant: INTEL CORPORATION

Inventor： CHARLES H. WALLACE ,  HOSSAM A. ABDALLAH ,  ELLIOT N. TAN ,  SWAMINATHAN SIVAKUMAR ,  OLEG GOLONZKA ,  ROBERT M. BIGWOOD

IPC: H01L23/00 ,  G03F1/36 ,  H01L21/027 ,  G03F1/70 ,  G03F7/00 ,  G03F7/40 ,  G03F7/20 ,  H01L21/02 ,  H01L21/263 ,  H01L27/02 ,  G03F1/50 ,  G03F7/16 ,  H01L21/306 ,  H01L21/308

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes.

公开(公告)号：US20190049514A1

公开(公告)日：2019-02-14

申请号：US16073688

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： KEVIN P. O'BRIEN ,  KAAN OGUZ ,  CHRISTOPHER J. WIEGAND ,  MARK L. DOCZY ,  BRIAN S. DOYLE ,  MD TOFIZUR RAHMAN ,  OLEG GOLONZKA ,  TAHIR GHANI

IPC: G01R31/28 ,  G01R31/315 ,  H01L21/66 ,  G01R33/09 ,  H01L43/12

CPC classification number: G01R31/2831 ,  G01N24/10 ,  G01R31/315 ,  G01R33/098 ,  G01R33/60 ,  G01R35/00 ,  H01L22/14 ,  H01L43/12

Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.