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公开(公告)号：US10209911B2
公开(公告)日：2019-02-19
申请号：US15024717
申请日：2014-09-16
Applicant: INTEL CORPORATION
Inventor： Jennifer Chin , Su Wei Lim , Poh Thiam Teoh , Ting Lok Song , Sun Zheng E , Say Cheong Gan
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.
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公开(公告)号：US20170083079A1
公开(公告)日：2017-03-23
申请号：US15370507
申请日：2016-12-06
Applicant: Intel Corporation
Inventor： Jennifer Chin , Su Wei Lim , Poh Thiam Teoh , Ting Lok Song , Sun Zheng E , Say Cheong Gan , Sujea Lim , Ming Yi Lim
CPC classification number: G06F1/3287 , G06F1/1626 , G06F1/3206 , G06F1/3218 , G06F1/3243 , G06F13/4282 , G06F2213/0026 , Y02D10/151 , Y02D10/152
Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
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3.发明授权Processor hiding its power-up latency with activation of a root port and quickly sending a downstream cycle 有权处理器通过激活根端口隐藏其上电延迟并快速发送下游周期公开(公告)号：US09563256B2
公开(公告)日：2017-02-07
申请号：US13734577
申请日：2013-01-04
Applicant: Intel Corporation
Inventor： Sun Zheng E , Ting Lok Song , Poh Thiam Teoh , Jennifer Chin , Say Cheong Gan , Sujea Lim , Su Wei Lim
IPC: G06F1/32
CPC classification number: G06F1/3253 , Y02D10/151 , Y02D50/20
Abstract: Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.
Abstract translation: 本文描述的特定实施例可以提供一种方法，其包括断电根端口; 通过中央处理单元（CPU）向根端口发起第一下游循环; 识别CPU的加电活动; 并且触发用于电力状态的退出流，同时向根端口发送第二下游循环。 在更具体的实施例中，用于功率状态的出口流的触发和将第二下游循环发送到根端口以基本上平行的方式发生。 另外，在CPU上电并发送第二个下游周期之前，可以将根据端口发送预取指示符以触发退出流。
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Patent Agency Ranking
公开(公告)号：US20180098320A1
公开(公告)日：2018-04-05
申请号：US15282411
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Say Cheong Gan , Poh Thiam Teoh , Kar HK Loo , Sun Zheng E , Keng Dar Ang
CPC classification number: H04W72/0446 , H04J3/0664 , H04L5/0055 , H04L43/106
Abstract: Aspects of the embodiments are directed to systems, methods, and devices, such as an upstream device that includes an input/output port. The input/output port configured to receive a message from an output port of a downstream device; transmit a plurality of acknowledgement messages to the downstream device; and transmit a response message to the received message to the downstream device.
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公开(公告)号：US09513662B2
公开(公告)日：2016-12-06
申请号：US13734612
申请日：2013-01-04
Applicant: Intel Corporation
Inventor： Jennifer Chin , Su Wei Lim , Poh Thiam Teoh , Ting Lok Song , Sun Zheng E , Say Cheong Gan , Sujea Lim , Ming Yi Lim
CPC classification number: G06F1/3287 , G06F1/1626 , G06F1/3206 , G06F1/3218 , G06F1/3243 , G06F13/4282 , G06F2213/0026 , Y02D10/151 , Y02D10/152
Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
Abstract translation: 本文描述的特定实施例可以提供一种用于管理至少一个处理器的功率的方法，该处理器包括评估与电子设备相关联的多个端口; 确定与所述端口中的至少一个相关联的特定引脚没有接收到信号; 禁用与所述电子设备相关联的静噪功能; 以及与电子设备的物理层（PHY）相关联的门控功率。
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公开(公告)号：US10257825B2
公开(公告)日：2019-04-09
申请号：US15282411
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Say Cheong Gan , Poh Thiam Teoh , Hooi Kar Loo , Sun Zheng E , Keng Dar Ang
Abstract: Aspects of the embodiments are directed to systems, methods, and devices, such as an upstream device that includes an input/output port. The input/output port configured to receive a message from an output port of a downstream device; transmit a plurality of acknowledgement messages to the downstream device; and transmit a response message to the received message to the downstream device.
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公开(公告)号：US10248183B2
公开(公告)日：2019-04-02
申请号：US15370507
申请日：2016-12-06
Applicant: Intel Corporation
Inventor： Jennifer Chin , Su Wei Lim , Poh Thiam Teoh , Ting Lok Song , Sun Zheng E , Say Cheong Gan , Sujea Lim , Ming Yi Lim
IPC: G06F1/32 , G06F1/3287 , G06F1/16 , G06F1/3206 , G06F1/3234 , G06F1/3218 , G06F13/42
Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
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公开(公告)号：US20160231958A1
公开(公告)日：2016-08-11
申请号：US15024717
申请日：2014-09-16
Applicant: INTEL CORPORATION
Inventor： Jennifer CHIN , Su Wei LIM , Poh Thiam TEOH , Ting Lok SONG , Sun Zheng E , Say Cheong GAN
CPC classification number: G06F3/0625 , G06F1/3237 , G06F1/3278 , G06F1/3287 , G06F3/061 , G06F3/0653 , G06F3/0673 , Y02D10/128 , Y02D10/157 , Y02D10/171
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.
Abstract translation: 各种实施例通常涉及用于确定通信端口何时处于第一低功率状态的装置，方法和其他技术，基于确定所述耦合设备进入低功率状态并启用第二低功率状态 器件已经进入低功耗状态，第二个低功耗状态使用比第一个低功耗状态更少的功率。
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