公开(公告)号：US09799610B2

公开(公告)日：2017-10-24

申请号：US14975360

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Mingjie Xu ,  Suzana Prstic ,  Kedar Dhane

IPC: H01L23/04 ,  H01L23/00 ,  H01L23/16

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L2924/3511

Abstract: Creating surface variations on a stiffener in a stack reduces inter-stiffener sticking and stiffener stack tilt in pick and place media. The surface variations provide one or more airgaps that reduce inter-stiffener surface contact, provide space for contaminants and/or provide an averaged surface height due to surface roughness.

公开(公告)号：US20170179043A1

公开(公告)日：2017-06-22

申请号：US14975360

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Mingjie Xu ,  Suzana Prstic ,  Kedar Dhane

IPC: H01L23/00 ,  H01L23/16

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L2924/3511

Abstract: Creating surface variations on a stiffener in a stack reduces inter-stiffener sticking and stiffener stack tilt in pick and place media. The surface variations provide one or more airgaps that reduce inter-stiffener surface contact, provide space for contaminants and/or provide an averaged surface height due to surface roughness.

公开(公告)号：US11652061B2

公开(公告)日：2023-05-16

申请号：US16442801

申请日：2019-06-17

Applicant: Intel Corporation

Inventor： Shenavia S. Howell ,  John J. Beatty ,  Raymond A. Krick ,  Suzana Prstic

IPC: H01L23/538 ,  H01L23/488 ,  H01L21/78 ,  H01L23/532

CPC classification number: H01L23/5386 ,  H01L21/7806 ,  H01L23/488 ,  H01L23/53242 ,  H01L23/53257

Abstract: Embodiments may relate to a microelectronic package that includes a die and a backside metallization (BSM) layer positioned on the face of the die. The BSM layer may include a feature that indicates that the BSM layer was formed on the face of the die by a masked deposition technique. Other embodiments may be described or claimed.

公开(公告)号：US20210035886A1

公开(公告)日：2021-02-04

申请号：US16529639

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065

Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

公开(公告)号：US20190006293A1

公开(公告)日：2019-01-03

申请号：US15638527

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： John J Beatty ,  Suzana Prstic ,  Vipul V Mehta

IPC: H01L23/00 ,  H01L23/34

Abstract: A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.

公开(公告)号：US11004768B2

公开(公告)日：2021-05-11

申请号：US16529639

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC: H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40

Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

公开(公告)号：US10290592B2

公开(公告)日：2019-05-14

申请号：US15638527

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： John J Beatty ,  Suzana Prstic ,  Vipul V Mehta

IPC: H01L23/00 ,  H01L23/34

Abstract: A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.