公开(公告)号：US20150056748A1

公开(公告)日：2015-02-26

申请号：US14505128

申请日：2014-10-02

Applicant: Intermolecular Inc.

Inventor： Pragati Kumar ,  Sean Barstow ,  Tony P. Chiang ,  Sunil Shanker

IPC: H01L45/00

CPC classification number: H01L45/1633 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.

公开(公告)号：US20140042384A1

公开(公告)日：2014-02-13

申请号：US14058518

申请日：2013-10-21

Applicant: Intermolecular Inc.

Inventor： Pragati Kumar ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G. Malhotra

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract translation: 包括电阻开关金属氧化物的非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US20130217200A1

公开(公告)日：2013-08-22

申请号：US13829378

申请日：2013-03-14

Applicant: Intermolecular Inc.

Inventor： Pragati KUMAR ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G. Malhotra

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US09030862B2

公开(公告)日：2015-05-12

申请号：US14488494

申请日：2014-09-17

Applicant: Intermolecular Inc.

Inventor： Pragati Kumar ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G Malhotra

IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L29/861

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract translation: 包括电阻开关金属氧化物的非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US20140256111A1

公开(公告)日：2014-09-11

申请号：US14281550

申请日：2014-05-19

Applicant: Intermolecular Inc.

Inventor： Sandra G. Malhotra ,  Sean Barstow ,  Tony P. Chiang ,  Wayne R. French ,  Pragati Kumar ,  Prashant B. Phatak ,  Sunil Shanker ,  Wen Wu

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。

公开(公告)号：US20140030887A1

公开(公告)日：2014-01-30

申请号：US14045100

申请日：2013-10-03

Applicant: Intermolecular Inc.

Inventor： Sean Barstow ,  Owen Ho Yin Fong

IPC: H01L21/768

CPC classification number: H01L21/76867 ,  C23C14/042 ,  C23C14/3464

Abstract: Provided are methods and systems for forming discreet multilayered structures. Each structure may be deposited by in situ deposition of multiple layers at one of multiple site isolation regions provided on the same substrate for use in combinatorial processing. Alignment of different layers within each structure is provided by using two or more differently sized openings in-between one or more sputtering targets and substrate. Specifically, deposition of a first layer is performed through the first opening that defines a first deposition area. A shutter having a second smaller opening is then positioned in-between the one or more targets and substrate. Sputtering of a second layer is then performed through this second opening that defines a second deposition area. This second deposition area may be located within the first deposition area based on sizing and alignment of the openings as well as alignment of the substrate.

Abstract translation: 提供形成谨慎的多层结构的方法和系统。 每个结构可以通过在设置在同一基底上的多个位置隔离区域之一的原位沉积多层来沉积，以用于组合处理。 通过在一个或多个溅射靶和衬底之间使用两个或更多个不同尺寸的开口来提供每个结构内的不同层的对准。 具体地，通过限定第一沉积区域的第一开口进行第一层的沉积。 然后将具有第二较小开口的闸板定位在一个或多个目标和基板之间。 然后通过限定第二沉积区域的该第二开口进行第二层的溅射。 基于开口的尺寸和对准以及衬底的对准，该第二沉积区域可以位于第一沉积区域内。

公开(公告)号：US08592282B2

公开(公告)日：2013-11-26

申请号：US13656585

申请日：2012-10-19

Applicant: Intermolecular, Inc.

Inventor： Sandra G. Malhotra ,  Sean Barstow ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B. Phatak ,  Sunil Shanker ,  Wen Wu

IPC: H01L21/02

CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

公开(公告)号：US20130109149A1

公开(公告)日：2013-05-02

申请号：US13725574

申请日：2012-12-21

Applicant: Intermolecular Inc.

Inventor： Sean Barstow ,  Tony P. Chiang ,  Pragati KUMAR ,  Sandra G. Malhotra

IPC: H01L45/00

CPC classification number: H01L45/1625 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以由电阻式开关金属氧化物层形成。 金属氧化物层可以使用相对低的溅射功率，相对低的占空比和较高的溅射气体压力的溅射沉积形成。 掺杂剂可以以小于基底氧化物中的掺杂剂的溶解度极限的原子浓度结合到基底氧化物层中。 基底氧化物中金属的至少一种氧化态优选不同于掺杂剂的至少一种氧化态。 可以选择掺杂剂的离子半径和金属的离子半径彼此接近。 可以对电阻式开关金属氧化物进行退火和氧化操作。 可以制造具有相对较大的电阻率和大的高 - 低 - 电阻率比的双稳态金属氧化物。

公开(公告)号：US09397292B2

公开(公告)日：2016-07-19

申请号：US14505128

申请日：2014-10-02

Applicant: Intermolecular Inc.

Inventor： Pragati Kumar ,  Sean Barstow ,  Tony P. Chiang ,  Sunil Shanker

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1633 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.

Abstract translation: 提供电阻式开关非易失性存储元件。 可以使用快速热退火技术来加热含金属层和用于存储元件的氧化物层。 在加热期间，氧化物层可能分解并与含金属层反应。 来自分解氧化物层的氧可以从含金属的层与金属形成金属氧化物。 所得到的金属氧化物可以表现出用于电阻式开关存储元件的电阻式开关。

公开(公告)号：US20160181380A1

公开(公告)日：2016-06-23

申请号：US14576597

申请日：2014-12-19

Applicant: Intermolecular Inc. ,  Global Foundries, Inc.

Inventor： Amol Joshi ,  Sean Barstow ,  Paul Besser ,  Ashish Bodke ,  Guillaume Bouche ,  Nobumichi Fuchigami ,  Zhendong Hong ,  Shaoming Koh ,  Albert Sanghyup Lee ,  Salil Mujumdar ,  Abhijit Pethe ,  Mark Victor Raymond

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L21/28568 ,  H01L21/02186 ,  H01L21/02362 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/76843 ,  H01L29/47 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7839

Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.

Abstract translation: 本文提供的实施例描述了用于形成半导体器件的系统和方法。 提供半导体衬底。 源极区和漏极区形成在半导体衬底上。 在源极区域和漏极区域之间形成栅电极。 在源极区域和漏极区域中的至少一个上方形成接触。 触点包括形成在半导体衬底之上的绝缘层，形成在绝缘层之上的界面层以及形成在界面层之上的金属层。 界面层可用作绝缘层的材料和金属层的材料之间的屏障，减小了绝缘层的材料与金属层的材料之间的电阻或其组合。