公开(公告)号：US11251182B2

公开(公告)日：2022-02-15

申请号：US16821604

申请日：2020-03-17

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ardasheir Rahman ,  Praveen Joseph ,  Indira Seshadri ,  Ekmini Anuja De Silva

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure includes a first semiconducting channel having a plurality of vertical nanowires and a second semiconducting channel having a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are configured to be in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are configured to be in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.

公开(公告)号：US20210234018A1

公开(公告)日：2021-07-29

申请号：US16776069

申请日：2020-01-29

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Ardasheir Rahman ,  Veeraraghavan S. Basker ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: A nanosheet FET has a substrate, an insulating layer disposed on the substrate, a source disposed on the insulating layer, and a drain disposed on the insulting layer. A plurality of parallel channels electrically and physically connects to and between the source and drain. One or more of the channels is separated from one or more adjacent and parallel channels by a suspension distance with two inner spacers. The inner spacers have three parts: a lower inner spacer, a middle inner spacer, and an upper inner spacer. The inner spacer design enables making the inner spacer using thinner layers of deposited dielectric material. The thinner deposition layers do not close the device spacing as much and enable smaller CRP while maintaining taller suspension distances.

公开(公告)号：US20200373413A1

公开(公告)日：2020-11-26

申请号：US16420530

申请日：2019-05-23

Applicant: International Business Machines Corporation

Inventor： Yi Song ,  Juntao Li ,  Huimei Zhou ,  Kangguo Cheng ,  Ardasheir Rahman

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/308 ,  H01L21/033

Abstract: A method of forming a semiconductor structure includes forming a fin over a substrate, forming a bottom source/drain over the substrate surrounding a first portion of sidewalls of the fin, and forming a bottom spacer over the bottom source/drain and surrounding a second portion of the sidewalls of the fin. The method also includes forming a T-shaped gate stack over the bottom spacer and surrounding a third portion of the sidewalls of the fin, forming a top spacer over the T-shaped gate stack and surrounding a fourth portion of the sidewalls of the fin, and forming a top source/drain over the top spacer and surrounding a fifth portion of the sidewalls and a top surface of the fin. The T-shaped gate stack includes a gate dielectric, a gate conductor, and a gate metal extending outward from a portion of sidewalls of the gate conductor between the bottom and top spacers.

公开(公告)号：US10325821B1

公开(公告)日：2019-06-18

申请号：US15840878

申请日：2017-12-13

Applicant: International Business Machines Corporation

Inventor： Terry Hook ,  Ardasheir Rahman ,  Joshua Rubin ,  Chen Zhang

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L23/00 ,  H01L29/78

Abstract: Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.

公开(公告)号：US20190181054A1

公开(公告)日：2019-06-13

申请号：US15840878

申请日：2017-12-13

Applicant: International Business Machines Corporation

Inventor： Terry Hook ,  Ardasheir Rahman ,  Joshua Rubin ,  Chen Zhang

IPC: H01L21/84 ,  H01L27/12 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L23/00

Abstract: Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.

公开(公告)号：US11956939B2

公开(公告)日：2024-04-09

申请号：US18183276

申请日：2023-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tsung-Sheng Kang ,  Ardasheir Rahman ,  Tao Li ,  Albert M. Young

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H10B10/00

CPC classification number: H10B10/12 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/7827

Abstract: A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

公开(公告)号：US20230320056A1

公开(公告)日：2023-10-05

申请号：US17657961

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： HUIMEI ZHOU ,  Carl Radens ,  MIAOMIAO WANG ,  Ardasheir Rahman

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L29/0665 ,  H01L21/823807

Abstract: Embodiments of present invention provide a static random-access-memory (SRAM) device. The SRAM device includes a first set of nanosheets used in an n-type transistor; and a second set of nanosheets with one or more nanosheets of the second set of nanosheets used in a p-type transistor, wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets. In one embodiment the p-type transistor is used as a pull-up transistor and the n-type transistor is used as a pull-down transistor or a pass-gate transistor. A method of manufacturing the SRAM device is also provided.

公开(公告)号：US20230207387A1

公开(公告)日：2023-06-29

申请号：US17563607

申请日：2021-12-28

Applicant: International Business Machines Corporation

Inventor： Sagarika Mukesh ,  Nicholas Anthony Lanzillo ,  Robert Robison ,  Ruqiang Bao ,  Ardasheir Rahman

IPC: H01L21/768 ,  H01L23/31

CPC classification number: H01L21/76832 ,  H01L23/3192 ,  H01L23/3171 ,  H01L21/76834 ,  H01L21/7682

Abstract: Embodiments of the present disclosure provide a semiconductor structure including a first metal contact, where at least a portion of the first metal contact extends vertically from a substrate to a top portion of the semiconductor structure. The first metal contact having an exposed surface at the top portion of the semiconductor structure. A dielectric cap may be configured around the first metal contact. The dielectric cap is configured to electrically separate a first area of the semiconductor structure from a second area of the semiconductor structure. The first area of the semiconductor structure includes the first metal contact.

公开(公告)号：US11678475B2

公开(公告)日：2023-06-13

申请号：US17381462

申请日：2021-07-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tsung-Sheng Kang ,  Ardasheir Rahman ,  Tao Li ,  Albert M. Young

IPC: H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/7827

Abstract: A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

公开(公告)号：US20220149042A1

公开(公告)日：2022-05-12

申请号：US17584801

申请日：2022-01-26

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ardasheir Rahman ,  Praveen Joseph ,  Indira Seshadri ,  Ekmini Anuja De Silva

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66

Abstract: A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.