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    Static random access memory using vertical transport field effect transistors
    4.
    发明授权
    Static random access memory using vertical transport field effect transistors 有权

    公开(公告)号：US11956939B2

    公开(公告)日：2024-04-09

    申请号：US18183276

    申请日：2023-03-14

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Tsung-Sheng Kang ,  Ardasheir Rahman ,  Tao Li ,  Albert M. Young

    IPC分类号： H01L27/11 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H10B10/00

    CPC分类号： H10B10/12 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/7827

    摘要： A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

    Static random access memory using vertical transport field effect transistors
    6.
    发明授权
    Static random access memory using vertical transport field effect transistors 有权

    公开(公告)号：US11678475B2

    公开(公告)日：2023-06-13

    申请号：US17381462

    申请日：2021-07-21

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Tsung-Sheng Kang ,  Ardasheir Rahman ,  Tao Li ,  Albert M. Young

    IPC分类号： H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L27/092

    CPC分类号： H01L27/1104 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/7827

    摘要： A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

    Self-Aligned Via to Metal Line for Interconnect
    8.
    发明申请
    Self-Aligned Via to Metal Line for Interconnect 有权

    公开(公告)号：US20230077878A1

    公开(公告)日：2023-03-16

    申请号：US17475995

    申请日：2021-09-15

    申请人： International Business Machines Corporation

    发明人： Tao Li ,  Ruilong Xie ,  Tsung-Sheng Kang ,  Alexander Reznicek

    IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

    摘要： Interconnect structures having top vias self-aligned to metal line ends and techniques for formation thereof are provided. In one aspect, an interconnect structure includes: at least one metal line disposed on a substrate; at least one top via over the at least one metal line, wherein the at least one top via is aligned with an end of the at least one metal line, and wherein a sidewall of the at least one top via is curved. A dielectric fill material can be disposed adjacent to the at least one top via having sidewalls that are also curved. A method of fabricating an interconnect structure is also provided.