-
公开(公告)号：US09037811B2
公开(公告)日：2015-05-19
申请号：US13835282
申请日：2013-03-15
CPC分类号： G06F13/16 , G06F3/0656 , G06F3/0659 , G06F13/1642 , G06F13/1689
摘要： Embodiments relate to tagging in a MCU. An aspect includes assigning a command tag to a command by a tag allocation logic of the MCU. Another aspect includes sending the command and the command tag on a plurality of channels that are in communication with the MCU. Another aspect includes receiving a response tag comprising one of a data tag and a done tag corresponding to the command tag from each of the plurality of channels. Another aspect includes, based on receiving a data tag from each of the plurality of channels, determining that read data corresponding to the command is available.
摘要翻译： 实施例涉及MCU中的标签。 一个方面包括通过MCU的标签分配逻辑将命令标签分配给命令。 另一方面包括在与MCU通信的多个信道上发送命令和命令标签。 另一方面包括从多个频道中的每一个接收包括与命令标签对应的数据标签和完成标签之一的响应标签。 另一方面包括：基于从多个通道中的每一个接收数据标签，确定对应于该命令的读取数据是可用的。
-
公开(公告)号：US20150121167A1
公开(公告)日：2015-04-30
申请号：US14098561
申请日：2013-12-06
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/10 , G06F11/1012 , G06F11/1048 , G06F11/1052 , G11C8/06 , G11C29/42 , G11C29/44 , G11C2029/0411
摘要： A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.
-
公开(公告)号：US08990641B2
公开(公告)日：2015-03-24
申请号：US13679593
申请日：2012-11-16
IPC分类号： G06F11/00
CPC分类号： G06F11/006 , G06F11/1004
摘要： In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.
摘要翻译： 在数据处理系统中，至少基于存储器子系统中的先前检测到的错误的地址，在关于目标存储器上的错误检测处理完成的数据传输的至少第一定时和第二定时之间进行选择 块的内存访问请求。 响应于存储器访问请求的接收和第一定时的选择，在对目标存储器块进行错误检测处理完成之前，来自目标存储器块的数据被发送到请求者。 响应于存储器访问请求的接收和第二定时的选择，来自目标存储器块的数据在对目标存储器块执行错误检测处理之后并且响应于完成对目标存储器块的错误检测处理而被发送到请求者。
-
公开(公告)号：US20140310472A1
公开(公告)日：2014-10-16
申请号：US14037021
申请日：2013-09-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0833 , G06F12/0864
摘要： In response to snooping a read-type memory access request of a requestor on a system fabric of a data processing system, a memory channel interface forwards the request to a memory buffer and starts a timer. In response to the forwarded request, the memory buffer performs a lookup of a target address of the request in a memory controller cache. In response to the target address hitting in a coherence state permitting provision of early data, the memory buffer provides a response indicating early data and provides a copy of a target memory block of the request to the memory channel interface. The memory channel interface, responsive to receipt prior to expiration of the timer of the response indicating early data, transmits the copy of the target memory block to the requestor via the system fabric prior to receiving a combined response of the data processing system to the request.
-
公开(公告)号：US10176125B2
公开(公告)日：2019-01-08
申请号：US15829516
申请日：2017-12-01
摘要： A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.
-
公开(公告)号：US09665346B2
公开(公告)日：2017-05-30
申请号：US14525313
申请日：2014-10-28
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
-
公开(公告)号：US09471410B2
公开(公告)日：2016-10-18
申请号：US14037792
申请日：2013-09-26
发明人： John S. Dodson , Benjiman L. Goodman , Guy L. Guthrie , Eric E. Retter , William J. Starke , Jeffrey A. Stuecheli
CPC分类号： G06F11/0751 , G06F11/073 , G06F11/1004
摘要： In a data processing system, a memory subsystem detects whether or not at least one potentially transient condition is present that would prevent timely servicing of one or more memory access requests directed to the associated system memory. In response to detecting at least one such potentially transient condition, the memory system identifies a first read request affected by the at least one potentially transient condition. In response to identifying the read request, the memory subsystem signals to a request source to issue a second read request for the same target address by transmitting to the request source dummy data and a data error indicator.
-
公开(公告)号：US09430418B2
公开(公告)日：2016-08-30
申请号：US13835485
申请日：2013-03-15
发明人： Patrick J. Meaney , Glenn D. Gilda , Eric E. Retter , John S. Dodson , Gary A. Van Huben , Brad W. Michael , Stephen J. Powell
CPC分类号： G06F11/1679 , G06F1/04 , G06F1/10 , G06F1/12 , G06F1/32 , G06F11/1497 , G06F11/1604 , G06F11/1675 , G06F13/1689 , G06F13/1694 , G11C7/1066 , G11C7/1072 , G11C7/1093 , G11C11/4076 , G11C11/4093 , G11C29/52
摘要： Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.
摘要翻译： 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。
-
公开(公告)号：US09176877B2
公开(公告)日：2015-11-03
申请号：US13862867
申请日：2013-04-15
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0833 , G06F12/0864
摘要： In response to snooping a read-type memory access request of a requestor on a system fabric of a data processing system, a memory channel interface forwards the request to a memory buffer and starts a timer. In response to the forwarded request, the memory buffer performs a lookup of a target address of the request in a memory controller cache. In response to the target address hitting in a coherence state permitting provision of early data, the memory buffer provides a response indicating early data and provides a copy of a target memory block of the request to the memory channel interface. The memory channel interface, responsive to receipt prior to expiration of the timer of the response indicating early data, transmits the copy of the target memory block to the requestor via the system fabric prior to receiving a combined response of the data processing system to the request.
摘要翻译： 响应于在数据处理系统的系统结构上窥探请求者的读取型存储器访问请求，存储器通道接口将请求转发到存储器缓冲器并启动定时器。 响应于转发的请求，存储器缓冲器在存储器控制器高速缓存中执行对请求的目标地址的查找。 响应于目标地址在允许提供早期数据的相干状态下触发，存储器缓冲器提供指示早期数据的响应，并将请求的目标存储器块的副本提供给存储器通道接口。 存储器通道接口响应于在指示早期数据的响应的定时器到期之前的接收，在接收到数据处理系统对请求的组合响应之前，经由系统结构将目标存储器块的副本发送到请求者 。
-
10.发明申请ECC BYPASS USING LOW LATENCY CE CORRECTION WITH RETRY SELECT SIGNAL 有权ECC BYPASS WITH LOW LATENCY CE CORRECTION WITH RETRY SELECT SIGNAL公开(公告)号：US20150121166A1
公开(公告)日：2015-04-30
申请号：US14062856
申请日：2013-10-24
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/10 , G06F11/1012 , G06F11/1048 , G06F11/1052 , G11C8/06 , G11C29/42 , G11C29/44 , G11C2029/0411
摘要： A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.
摘要翻译： 存储器控制器配备有用于不同复杂度错误水平的多个纠错电路，但是请求的数据最初经由提供最低存储器延迟的旁路路径发送到请求单元（例如，处理器）。 请求单元执行错误检测，并且如果发现错误，则将重试选择信号发送到存储器控制器。 重试选择信号提供了哪个错误校正单元应该用于提供错误的完整校正的指示，但是添加最小等待时间。 在重试传输中，控制器使用由重试选择信号指示的特定纠错单元。 存储器控制器还可以具有持续错误检测电路，其在由多个重试选择信号重复指示错误时将地址标识为有缺陷，并且控制逻辑可以使用适当的纠错单元自动发送所请求的数据。
-
-
-
-
-
-
-
-
-
搜索结果
42 条记录 (耗时 0.028 秒)
