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    Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection
    1.
    发明授权
    Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection 有权

    公开(公告)号：US10541782B2

    公开(公告)日：2020-01-21

    申请号：US15817416

    申请日：2017-11-20

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

    IPC: H04L1/00 ,  H03M13/09

    Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

    Use of multiple cyclic redundancy codes for optimized fail isolation
    2.
    发明授权
    Use of multiple cyclic redundancy codes for optimized fail isolation 有权

    公开(公告)号：US10419035B2

    公开(公告)日：2019-09-17

    申请号：US15817399

    申请日：2017-11-20

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

    IPC: H03M13/00 ,  H03M13/35 ,  H04L1/00

    Abstract: Aspects of the invention include calculating, by a transmitter, source cyclic redundancy code (CRC) bits for payload bits. The source CRC bits include source CRC bits for a first type of CRC check and source CRC bits for a second type of CRC check. The source CRC bits are stored at the transmitter. The payload bits and the source CRC bits for the first type of CRC check are transmitted to the receiver. The receiver performs the first type of CRC check based at least in part on the payload bits and the source CRC bits for the first type of CRC check. The receiver also calculates and stores at the receiver calculated CRC bits for the second type of CRC check. If the first type of CRC check indicates an error, a comparison of the source and calculated CRC bits for the second type of CRC check is initiated.

    Scalable data collection for system management
    3.
    发明授权
    Scalable data collection for system management 有权
    可扩展的数据收集系统管理

    公开(公告)号：US09250666B2

    公开(公告)日：2016-02-02

    申请号：US13686391

    申请日：2012-11-27

    Applicant: International Business Machines Corporation

    Inventor： Irving Baysah ,  John S. Dodson ,  Karthick Rajamani ,  Eric E. Retter ,  Gregory S. Still ,  Malcolm S. Allen-Ware ,  Scot H. Rider ,  Todd J. Rosedahl ,  Gary Van Huben

    IPC: G06F1/20 ,  G06F1/32

    CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F11/3037 ,  G06F11/3409 ,  Y02D10/11 ,  Y02D10/16

    Abstract: A system with scalable data collection for system management comprises a plurality of local data collectors and a system collector. Each of the local data collectors is coupled with a corresponding subsystem of the system. Each of the local data collectors is configured to periodically collect power management related data from the corresponding subsystem, and to format the collected power management related data for conveyance along any one of a plurality of channels between the local data collector and the system collector. The system collector is coupled with the plurality of local data collectors via the plurality of channels. The system collector selects from the channels between the system collector and each of the local data collectors based, at least in part, on channel states, and retrieves the power management related data collected by each of the local data collectors along a selected channel for the local data collector.

    Abstract translation: 具有用于系统管理的可扩展数据收集的系统包括多个本地数据收集器和系统收集器。 每个本地数据采集器与系统的相应子系统耦合。 每个本地数据收集器被配置为周期性地从相应的子系统收集功率管理相关数据，并且格式化收集的功率管理相关数据，以便沿着本地数据采集器和系统收集器之间的多个通道中的任一个传送。 系统收集器经由多个通道与多个本地数据收集器耦合。 系统收集器至少部分地基于信道状态从系统收集器和每个本地数据收集器之间的信道中选择，并且沿着所选择的信道检索由每个本地数据收集器收集的功率管理相关数据，用于 本地数据收集器。

    Dynamically adjustable cyclic redundancy code rates
    4.
    发明授权
    Dynamically adjustable cyclic redundancy code rates 有权

    公开(公告)号：US10530523B2

    公开(公告)日：2020-01-07

    申请号：US15817408

    申请日：2017-11-20

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

    IPC: H04L1/18 ,  H04L1/00 ,  H04L1/20

    Abstract: Aspects of the invention include receiving a specified number of frames of bits at a receiver. At least one of the received frames includes cyclic redundancy code (CRC) bits. The specified number of frames is based at least in part on a CRC rate. It is determined, by performing a CRC check on the received frames, whether a change in transmission errors has occurred in the received frames. An increase in the CRC rate is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred in the received frames. The increase in the CRC rate is synchronized between the receiver and the transmitter; and performed in parallel with functional operations performed by the receiver.

    USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PROVIDE EARLY WARNING AND FAIL DETECTION
    7.
    发明申请
    USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PROVIDE EARLY WARNING AND FAIL DETECTION 审中-公开

    公开(公告)号：US20190158223A1

    公开(公告)日：2019-05-23

    申请号：US15817416

    申请日：2017-11-20

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

    IPC: H04L1/00

    Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

    Functional built-in self test for a chip
    8.
    发明授权
    Functional built-in self test for a chip 有权
    功能内置自检芯片

    公开(公告)号：US09384108B2

    公开(公告)日：2016-07-05

    申请号：US13693236

    申请日：2012-12-04

    Applicant: International Business Machines Corporation

    Inventor： Kevin M. McIlvain ,  Robert B. Tremaine ,  Gary Van Huben

    IPC: G06F9/455 ,  G01R31/28 ,  G06F11/00 ,  G06F11/27

    CPC classification number: G06F11/27

    Abstract: According to one embodiment, a self-test system integrated on a chip is provided, the chip including a functional logic module for performing a selected application. The self-test system includes a primary interface a primary interface to the functional logic module, the primary interface configured to interface with a primary device, an input interface protocol generator for generating a pattern to be inserted into the primary interface and a secondary interface to the functional logic module, the secondary interface configured to interface with a secondary device. The system also includes an emulator engine coupled to the secondary interface, the emulator engine for testing a function of the functional logic module based on the inserted patterns, the function being configured to communicate with a secondary device coupled to the secondary interface, wherein the emulator engine tests the function when no secondary device is coupled to the chip.

    Abstract translation: 根据一个实施例，提供集成在芯片上的自检系统，该芯片包括用于执行所选应用的功能逻辑模块。 所述自检系统包括主界面，功能逻辑模块的主界面，被配置为与主设备接口的主界面，用于生成要插入到主界面中的模式的输入接口协议生成器，以及辅助接口 功能逻辑模块，辅助接口配置为与辅助设备进行接口。 该系统还包括耦合到辅助接口的仿真器引擎，用于基于所插入的模式来测试功能逻辑模块的功能的仿真器引擎，该功能被配置为与耦合到辅助接口的辅助设备进行通信，其中仿真器 引擎在没有辅助设备耦合到芯片时测试功能。

    SCALABLE DATA COLLECTION FOR SYSTEM MANAGEMENT
    9.
    发明申请
    SCALABLE DATA COLLECTION FOR SYSTEM MANAGEMENT 有权
    可扩展数据收集系统管理

    公开(公告)号：US20140149751A1

    公开(公告)日：2014-05-29

    申请号：US13686391

    申请日：2012-11-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Irving Baysah ,  John S. Dodson ,  Karthick Rajamani ,  Eric E. Retter ,  Gregory S. Still ,  Malcolm S. Allen-Ware ,  Scot H. Rider ,  Todd J. Rosedahl ,  Gary Van Huben

    IPC: G06F1/26

    CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F11/3037 ,  G06F11/3409 ,  Y02D10/11 ,  Y02D10/16

    Abstract: A system with scalable data collection for system management comprises a plurality of local data collectors and a system collector. Each of the local data collectors is coupled with a corresponding subsystem of the system. Each of the local data collectors is configured to periodically collect power management related data from the corresponding subsystem, and to format the collected power management related data for conveyance along any one of a plurality of channels between the local data collector and the system collector. The system collector is coupled with the plurality of local data collectors via the plurality of channels. The system collector selects from the channels between the system collector and each of the local data collectors based, at least in part, on channel states, and retrieves the power management related data collected by each of the local data collectors along a selected channel for the local data collector.

    Abstract translation: 具有用于系统管理的可扩展数据收集的系统包括多个本地数据收集器和系统收集器。 每个本地数据采集器与系统的相应子系统耦合。 每个本地数据收集器被配置为周期性地从相应的子系统收集功率管理相关数据，并且格式化收集的功率管理相关数据，以便沿着本地数据采集器和系统收集器之间的多个通道中的任一个传送。 系统收集器经由多个通道与多个本地数据收集器耦合。 系统收集器至少部分地基于信道状态从系统收集器和每个本地数据收集器之间的信道中选择，并且沿着所选择的信道检索由每个本地数据收集器收集的功率管理相关数据，用于 本地数据收集器。

    Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection
    10.
    发明授权
    Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection 有权

    公开(公告)号：US11088782B2

    公开(公告)日：2021-08-10

    申请号：US16715162

    申请日：2019-12-16

    Applicant: International Business Machines Corporation

    Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

    IPC: H04L1/00 ,  H03M13/09

    Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

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