公开(公告)号：US20150311283A1

公开(公告)日：2015-10-29

申请号：US14734713

申请日：2015-06-09

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James R. Elliott ,  David L. Harame ,  Marwan H. Khater ,  Robert K. Leidy ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/732

CPC classification number: H01L29/0649 ,  H01L29/045 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66257 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7325 ,  H01L29/7375

Abstract: Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract translation: 双极结型晶体管的器件结构。 器件结构包括集电极区域，形成在集电极区域上的本征基极，与本征基极耦合并与集电极与本征基极分离的发射极，以及延伸穿过本征基极到集电极区域的隔离区域。 隔离区形成有具有延伸穿过本征基底的第一侧壁的第一部分和具有延伸到收集器区域中的第二侧壁的第二部分。 第二侧壁相对于第一侧壁倾斜。 隔离区域位于形成有第一和第二蚀刻工艺的沟槽中，其中后者以不同的蚀刻速率蚀刻单晶半导体材料的不同晶体方向。

公开(公告)号：US20150123245A1

公开(公告)日：2015-05-07

申请号：US14070989

申请日：2013-11-04

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/66 ,  H01L29/732

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

公开(公告)号：US09224843B2

公开(公告)日：2015-12-29

申请号：US14673958

申请日：2015-03-31

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Qizhi Liu

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/306 ,  H01L21/465 ,  H01L21/762 ,  H01L29/165 ,  H01L29/732

CPC classification number: H01L29/7371 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/465 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.

公开(公告)号：US20150108549A1

公开(公告)日：2015-04-23

申请号：US14059780

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/465 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.

公开(公告)号：US09274277B2

公开(公告)日：2016-03-01

申请号：US14278689

申请日：2014-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brennan J. Brown ,  James R. Elliott ,  Qizhi Liu ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/132 ,  G02B6/136 ,  H01L31/0232 ,  H01L33/58

CPC classification number: G02B6/125 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B2006/12061 ,  H01L31/02327 ,  H01L33/58

Abstract: Si waveguide devices on a bulk Si substrate with supporting anchors and methods of manufacture are disclosed. The method includes forming a waveguide device over an Si substrate, and forming one or more anchors from the Si substrate. The one or more anchors support the waveguide device.

Abstract translation: 公开了具有支撑锚固体和制造方法的体积Si衬底上的Si波导器件。 该方法包括在Si衬底上形成波导器件，并从Si衬底形成一个或多个锚固件。 一个或多个锚固件支撑波导装置。

公开(公告)号：US20150214344A1

公开(公告)日：2015-07-30

申请号：US14677303

申请日：2015-04-02

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

Abstract translation: 双极结型晶体管的器件结构，设计结构和制造方法。 由包含第一半导体材料的第一层和由第二半导体材料构成的第二层设置在包含双极结型晶体管的第一端子的衬底上。 第二层设置在第一层上，并且在第二层上形成图案化的蚀刻掩模。 沟槽延伸穿过图案硬掩模层，第一层和第二层并进入衬底。 沟槽限定了与第二层的一部分堆叠的第一层的一部分。 使用选择性蚀刻工艺来相对于第一层的截面来缩小第二层的截面以限定第二端子并且加宽衬底中的沟槽的一部分以削弱第一层的部分。

公开(公告)号：US09093491B2

公开(公告)日：2015-07-28

申请号：US13705717

申请日：2012-12-05

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James R. Elliott ,  David L. Harame ,  Marwan H. Khater ,  Robert K. Leidy ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L21/8222 ,  H01L29/73 ,  H01L29/737 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0649 ,  H01L29/045 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66257 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7325 ,  H01L29/7375

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 器件结构包括集电极区域，形成在集电极区域上的本征基极，与本征基极耦合并与集电极与本征基极分离的发射极，以及延伸穿过本征基极到集电极区域的隔离区域。 隔离区形成有具有延伸穿过本征基底的第一侧壁的第一部分和具有延伸到收集器区域中的第二侧壁的第二部分。 第二侧壁相对于第一侧壁倾斜。 隔离区域位于形成有第一和第二蚀刻工艺的沟槽中，其中后者以不同的蚀刻速率蚀刻单晶半导体材料的不同晶体方向。

公开(公告)号：US20150206959A1

公开(公告)日：2015-07-23

申请号：US14673958

申请日：2015-03-31

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/165 ,  H01L29/06 ,  H01L29/732

CPC classification number: H01L29/7371 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/465 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.

Abstract translation: 公开了沟槽形成技术，其中第一蚀刻工艺形成通过半导体层进入半导体衬底的开口，然后第二蚀刻工艺扩展衬底内部的开口部分以形成沟槽。 然而，在第二蚀刻之前，在开口的底表面处的衬底中形成掺杂区域。 然后，进行第二蚀刻，使得在开口侧壁处的衬底的未掺杂区域以比掺杂区更快的蚀刻速率被蚀刻，从而确保沟槽具有相对高的纵横比。 还公开了一种双极半导体器件形成方法。 该方法结合沟槽形成技术，使得围绕集电极基座形成的沟槽隔离区域具有高纵横比，从而使集电极到基极电容Ccb和集电极电阻Rc都最小化。

公开(公告)号：US09240448B2

公开(公告)日：2016-01-19

申请号：US14734713

申请日：2015-06-09

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James R. Elliott ,  David L. Harame ,  Marwan H. Khater ,  Robert K. Leidy ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/0649 ,  H01L29/045 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66257 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7325 ,  H01L29/7375

Abstract: Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract translation: 双极结型晶体管的器件结构。 器件结构包括集电极区域，形成在集电极区域上的本征基极，与本征基极耦合并与集电极与本征基极分离的发射极，以及延伸穿过本征基极到集电极区域的隔离区域。 隔离区形成有具有延伸穿过本征基底的第一侧壁的第一部分和具有延伸到收集器区域中的第二侧壁的第二部分。 第二侧壁相对于第一侧壁倾斜。 隔离区域位于形成有第一和第二蚀刻工艺的沟槽中，其中后者以不同的蚀刻速率蚀刻单晶半导体材料的不同晶体方向。

公开(公告)号：US09059234B2

公开(公告)日：2015-06-16

申请号：US14059780

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Qizhi Liu

IPC: H01L21/265 ,  H01L21/306 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06 ,  H01L21/465 ,  H01L21/762

CPC classification number: H01L29/7371 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/465 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.

Abstract translation: 公开了沟槽形成技术，其中第一蚀刻工艺形成通过半导体层进入半导体衬底的开口，然后第二蚀刻工艺扩展衬底内部的开口部分以形成沟槽。 然而，在第二蚀刻之前，在开口的底表面处的衬底中形成掺杂区域。 然后，进行第二蚀刻，使得在开口侧壁处的衬底的未掺杂区域以比掺杂区更快的蚀刻速率被蚀刻，从而确保沟槽具有相对高的纵横比。 还公开了一种双极半导体器件形成方法。 该方法结合沟槽形成技术，使得围绕集电极基座形成的沟槽隔离区域具有高纵横比，从而使集电极到基极电容Ccb和集电极电阻Rc都最小化。