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公开(公告)号：US20240178292A1
公开(公告)日：2024-05-30
申请号：US17994487
申请日：2022-11-28
IPC分类号： H01L29/423 , H01L27/088 , H01L29/06 , H01L29/417 , H01L29/66 , H01L29/775
CPC分类号： H01L29/42392 , H01L27/088 , H01L29/0673 , H01L29/41775 , H01L29/66553 , H01L29/775
摘要： A semiconductor structure is presented including semiconductor layers of a first nanosheet stack, semiconductor layers of a second nanosheet stack formed over and having a stepped nanosheet formation with respect to the semiconductor layers of the first nanosheet stack, a first epitaxial growth formed adjacent the semiconductor layers of the first nanosheet stack, and a second epitaxial growth formed adjacent the semiconductor layers of the second nanosheet stack such that the second epitaxial growth has a stepped formation with respect to the first epitaxial growth. The second epitaxial growth has a volume greater than a volume of the first epitaxial growth.
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公开(公告)号：US20240162319A1
公开(公告)日：2024-05-16
申请号：US18054958
申请日：2022-11-14
IPC分类号： H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0673 , H01L29/66545 , H01L29/78696
摘要： Embodiments of the invention include a stacked device having a first epitaxial region and a second epitaxial region vertically displaced from the first epitaxial region. The first epitaxial region comprising an asymmetric profile with a horizontal protrusion. A contact is formed on the horizontal protrusion of the first epitaxial region
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公开(公告)号：US20240071811A1
公开(公告)日：2024-02-29
申请号：US17822173
申请日：2022-08-25
发明人： Su Chen Fan , Jay William Strane , Gen Tsutsui , Stuart Sieg
IPC分类号： H01L21/762 , H01L21/8238 , H01L25/065 , H01L29/06 , H01L29/786
CPC分类号： H01L21/76235 , H01L21/823807 , H01L25/0657 , H01L29/0653 , H01L29/78696
摘要： A stacked field effect transistor (FET) device. The device includes an opening in a shallow trench isolation (STI) region on a substrate. The device also includes an epitaxy region located on the substrate at a bottom portion of STI region in the opening. The device further includes a substrate contact that directly contacts the epitaxy region.
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公开(公告)号：US20210320186A1
公开(公告)日：2021-10-14
申请号：US16847938
申请日：2020-04-14
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/78
摘要： Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.
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公开(公告)号：US20210217889A1
公开(公告)日：2021-07-15
申请号：US16738152
申请日：2020-01-09
IPC分类号： H01L29/78 , H01L29/06 , H01L29/417 , H01L29/66
摘要： A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.
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公开(公告)号：US20240203984A1
公开(公告)日：2024-06-20
申请号：US18067968
申请日：2022-12-19
发明人： Su Chen Fan , Indira Seshadri , Jay William Strane , Stuart Sieg
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/06 , H01L29/423 , H01L29/775
CPC分类号： H01L27/088 , H01L21/823412 , H01L29/0673 , H01L29/42392 , H01L29/775
摘要： Semiconductor devices and methods of forming the same include a lower semiconductor device over a substrate, the lower semiconductor device having a first width. An upper semiconductor device is over the lower semiconductor device. The upper semiconductor device has a second width smaller than the first width. A dielectric structure is over the lower semiconductor device and has a first sidewall that faces the upper semiconductor device and a second sidewall that aligns vertically with a sidewall of the lower semiconductor device.
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公开(公告)号：US20240186324A1
公开(公告)日：2024-06-06
申请号：US18061526
申请日：2022-12-05
发明人： Albert M. Chu , Junli Wang , Jay William Strane
IPC分类号： H01L27/092 , H01L29/423
CPC分类号： H01L27/0922 , H01L29/42324 , H01L29/42356 , H03K3/356104
摘要： A semiconductor structure is presented having a first field effect transistor (FET) including a first device layer, a second FET including a second device layer, where the first device layer has a stepped portion with respect to the second device layer, and an electrical connection between a gate of the first FET and a gate of the second FET at the stepped portion of the first device layer. The first FET is stacked over the second FET. The second device layer is larger than the first device layer. The gate of the first FET is positioned above the first device layer having a stepped portion.
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公开(公告)号：US20230395596A1
公开(公告)日：2023-12-07
申请号：US17805039
申请日：2022-06-02
发明人： Su Chen Fan , Dominik Metzler , Hemanth Jagannathan , Jing Guo , Jay William Strane , Ruilong Xie
IPC分类号： H01L27/088 , H01L27/12 , H01L23/532 , H01L23/522
CPC分类号： H01L27/088 , H01L27/124 , H01L27/1248 , H01L23/5329 , H01L23/5226
摘要： A semiconductor structure including a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor, where at least one vertical surface of the first top contact is substantially flush with at least one vertical surface of the isolation region, and where at least one vertical surface of the second top contact is substantially flush with the at least one vertical surface of the isolation region.
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公开(公告)号：US11646373B2
公开(公告)日：2023-05-09
申请号：US17516994
申请日：2021-11-02
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/417
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/41791 , H01L29/66666 , H01L29/66795 , H01L29/785
摘要： A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.
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公开(公告)号：US11251287B2
公开(公告)日：2022-02-15
申请号：US16847938
申请日：2020-04-14
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8234
摘要： Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.
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