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1.发明授权公开(公告)号：US11894436B2
公开(公告)日：2024-02-06
申请号：US17543028
申请日：2021-12-06
发明人： Julien Frougier , Ruilong Xie , Nicolas Loubet , Andrew M. Greene , Veeraraghavan S. Basker , Balasubramanian S. Pranatharthiharan
IPC分类号： H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0673 , H01L29/66545 , H01L29/78696
摘要： A CFET (complementary field effect transistor) structure including a substrate, a first CFET formed above the substrate, and a second CFET formed above the substrate. The first CFET includes a top FET and a bottom FET. The top FET and bottom FET of the first CFET include at least one nanosheet channel. A gate affiliated with the first CFET and the second CFET devices includes a continuous horizontal dielectric over the entire length of the gate. The top FET of each CFET has a first polarity. The bottom FET of each a CFET comprises a second polarity. The top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal.
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公开(公告)号：US20230238236A1
公开(公告)日：2023-07-27
申请号：US17586757
申请日：2022-01-27
发明人： Cornelius Brown Peethala , Rudy J. Wojtecki , SON NGUYEN , Balasubramanian S. Pranatharthiharan
IPC分类号： H01L21/02 , H01L23/522
CPC分类号： H01L21/02263 , H01L21/02118 , H01L23/5226
摘要： An exemplary semiconductor structure includes a semiconductor substrate; a plurality of metal lines on top of the semiconductor substrate, each line having a line width 5 nanometers or less: a plurality of dielectric features adjacent to the metal lines; and a plurality of metal vias on top of the metal lines. Out of a random sample of 1000 vias at least 950 vias are fully-aligned to corresponding metal lines.
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公开(公告)号：US09397006B1
公开(公告)日：2016-07-19
申请号：US14959407
申请日：2015-12-04
IPC分类号： H01L21/336 , H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/10
CPC分类号： H01L21/823431 , H01L21/823412 , H01L27/0886 , H01L29/1083 , H01L29/66545 , H01L29/6656
摘要： A method includes forming a first set of fins on a substrate; forming a second set of fins on the substrate; forming a gate stack over the fins and substrate; depositing a spacer layer around each fin in the first set of fins and in the second set of fins and the substrate; etching horizontal and vertical surfaces covered by the spacer layer to form spacers around the first set of fins and the second set of fins; etching horizontal and vertical surfaces of the spacer to pull down the spacer around the second set of fins; growing an epitaxy layer around the first set of fins and the second set of fins and growing epitaxy on the first set of fins and on the second set of fins; merging the epitaxy on the first set of fins; and merging the epitaxy on the second set of fins.
摘要翻译： 一种方法包括在基底上形成第一组翅片; 在所述基板上形成第二组翅片; 在所述翅片和基底上形成栅叠层; 在第一组翅片和第二组翅片和基底中的每个翅片周围沉积间隔层; 蚀刻由间隔层覆盖的水平和垂直表面，以围绕第一组翅片和第二组翅片形成间隔物; 蚀刻间隔物的水平和垂直表面以使间隔件围绕第二组翅片下拉; 围绕第一组翅片和第二组翅片生长外延层，并且在第一组翅片上和第二组翅片上生长外延; 将外延合并在第一组翅片上; 并将外延合并在第二组翅片上。
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公开(公告)号：US20160148872A1
公开(公告)日：2016-05-26
申请号：US14828639
申请日：2015-08-18
IPC分类号： H01L23/535 , H01L27/088 , H01L27/02
CPC分类号： H01L23/535 , H01L21/31056 , H01L21/76843 , H01L21/76865 , H01L21/76877 , H01L21/76897 , H01L23/485 , H01L23/53266 , H01L27/0207 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including at least one self-aligned contact has at least one gate electrode on a bulk substrate layer of the semiconductor device. A gate cap encapsulates the at least one gate electrode. The semiconductor device further includes at least one contact separated from the at least one gate electrode via a portion of the gate cap. The at least one contact includes a metal portion that directly contacts the gate cap.
摘要翻译： 包括至少一个自对准接触的半导体器件在半导体器件的体基底层上具有至少一个栅电极。 栅极帽封装至少一个栅电极。 半导体器件还包括经由栅极盖的一部分与至少一个栅电极分开的至少一个触点。 至少一个触点包括直接接触栅极盖的金属部分。
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公开(公告)号：US20230290823A1
公开(公告)日：2023-09-14
申请号：US17654607
申请日：2022-03-14
IPC分类号： H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L29/417 , H01L21/8234 , H01L21/768
CPC分类号： H01L29/0665 , H01L29/42392 , H01L29/78618 , H01L29/78696 , H01L29/66553 , H01L29/41733 , H01L21/823412 , H01L21/76843
摘要： A semiconductor device including a nanodevice located on a substrate, where the nanodevice includes a plurality of nanosheets. Each of the plurality of nanosheets are spaced apart from each other by a first distance. A gate located on the substrate, where the gate surrounds each of the plurality of nanosheets. A first dielectric layer located on the substrate, where the first dielectric layer is located adjacent to a sidewall of the gate. The gate has a first thickness when measured from the sidewall of one of the plurality of nanosheets to a sidewall of the first dielectric layer, where the first thickness is larger than the first distance. An inner spacer located on the substrate, where the inner spacer is wraps around an end of each of the plurality of nanosheets. The inner spacer has a second thickness, where the second thickness is substantially equal to the first distance.
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公开(公告)号：US20230207553A1
公开(公告)日：2023-06-29
申请号：US17562331
申请日：2021-12-27
发明人： Ruilong Xie , Kisik Choi , Somnath Ghosh , Sagarika Mukesh , Albert Chu , Albert M. Young , Balasubramanian S. Pranatharthiharan , Huiming Bu , Kai Zhao , John Christopher Arnold , Brent A. Anderson , Dechao Guo
IPC分类号： H01L27/02 , H01L29/423 , H01L29/06 , H01L27/092 , H01L27/12 , H01L21/8234 , H01L21/762
CPC分类号： H01L27/0207 , H01L29/42392 , H01L29/0673 , H01L27/092 , H01L27/1251 , H01L21/823475 , H01L21/76229
摘要： A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.
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公开(公告)号：US10347749B2
公开(公告)日：2019-07-09
申请号：US15469237
申请日：2017-03-24
IPC分类号： H01L29/66 , H01L21/762
摘要： A first layer of a first material is deposited on a first structure and a second structure, a surface of the first structure being disposed substantially parallelly to a surface of the second structure in at least one direction. A selectively removable material is deposited over the first layer and removed up to a height of a first step. The first material is removed from a portion of the first layer that is exposed from removing the selectively removable material up to the height of the first step. A remainder of the selectively removable material is removed to expose a second portion of the first layer, the second portion of the first layer forming the first step. A second layer of a second material is deposited on the first structure, the second structure, and the second portion of the first layer, causing a formation of a stepped structure.
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公开(公告)号：US10224326B2
公开(公告)日：2019-03-05
申请号：US15608545
申请日：2017-05-30
发明人： Andrew M. Greene , Balasubramanian S. Pranatharthiharan , Sivananda K. Kanakasabapathy , John R. Sporre
IPC分类号： H01L29/06 , H01L27/088 , H01L29/66 , H01L29/78 , H01L29/161 , H01L21/308 , H01L21/027 , H01L21/8234 , H01L21/8238 , H01L27/12
摘要： A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
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公开(公告)号：US09627322B2
公开(公告)日：2017-04-18
申请号：US14828639
申请日：2015-08-18
IPC分类号： H01L23/535 , H01L21/768 , H01L21/3105 , H01L23/485 , H01L23/532 , H01L27/02 , H01L27/088
CPC分类号： H01L23/535 , H01L21/31056 , H01L21/76843 , H01L21/76865 , H01L21/76877 , H01L21/76897 , H01L23/485 , H01L23/53266 , H01L27/0207 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including at least one self-aligned contact has at least one gate electrode on a bulk substrate layer of the semiconductor device. A gate cap encapsulates the at least one gate electrode. The semiconductor device further includes at least one contact separated from the at least one gate electrode via a portion of the gate cap. The at least one contact includes a metal portion that directly contacts the gate cap.
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公开(公告)号：US09576954B1
公开(公告)日：2017-02-21
申请号：US14862258
申请日：2015-09-23
IPC分类号： H01L27/092 , H01L29/772 , H01L27/088 , H01L21/8234 , H01L29/66 , H01L21/3105 , H01L21/311 , H01L21/762 , H01L29/06
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02167 , H01L21/0217 , H01L21/0332 , H01L21/31053 , H01L21/31116 , H01L21/31144 , H01L21/76205 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823864 , H01L27/0886 , H01L29/0649 , H01L29/42368 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66795
摘要： A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.
摘要翻译： 在栅极之间填充沟槽的方法包括在衬底上形成第一和第二虚拟栅极，第一和第二伪栅极包括牺牲栅极材料和硬掩模层; 沿着第一伪栅极的侧壁形成第一栅极间隔物，沿着第二虚拟栅极的侧壁形成第二栅极间隔物; 执行外延生长工艺以在第一和第二虚拟栅极之间的衬底上形成源极/漏极; 在第一和第二伪栅极和源极/漏极上设置保形衬垫; 在第一和第二伪栅极之间的保形衬垫上设置氧化物; 将氧化物凹陷到低于第一和第二伪栅极的硬掩模层的水平以形成凹陷氧化物; 以及在第一伪栅极和第二虚拟栅极之间的凹陷氧化物上沉积间隔物材料。
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