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公开(公告)号：US20040137689A1
公开(公告)日：2004-07-15
申请号：US10345472
申请日：2003-01-15
IPC分类号： H01L021/336
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.
摘要翻译： 低GIDL电流MOSFET器件结构及其制造方法，其提供低GIDL电流。 MOSFET器件结构包含中心栅极导体，其边缘可能与源极/漏极扩散稍微重叠，以及通过薄的绝缘和扩散阻挡层与中心栅极导体分离的左侧和右侧翼栅极导体。
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公开(公告)号：US20040129941A1
公开(公告)日：2004-07-08
申请号：US10338071
申请日：2003-01-07
IPC分类号： H01L029/76
CPC分类号： B82Y30/00 , B82Y10/00 , B82Y20/00 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/0332 , H01L21/0337 , H01L31/0352
摘要： A method for forming a uniform layered structure comprising an ultra-thin layer of amorphous silicon and its thermal oxide is disclosed. In one aspect, a method for forming a nanolaminate of silicon oxide on a substrate is disclosed. In another aspect, a method for forming a patterned hard mask on a substrate is disclosed. The patterned hard mask includes a nanolaminate of silicon and silicon oxide. The methods are characterized by the oxidation of an amorphous silicon layer using atomic oxygen.
摘要翻译： 公开了一种用于形成均匀层状结构的方法，其包括非晶硅超薄层及其热氧化物。 一方面，公开了一种在衬底上形成氧化硅的纳米氨酸盐的方法。 另一方面，公开了一种在衬底上形成图案化硬掩模的方法。 图案化的硬掩模包括硅和氧化硅的纳米氨酸盐。 该方法的特征在于使用原子氧氧化非晶硅层。
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公开(公告)号：US20040113207A1
公开(公告)日：2004-06-17
申请号：US10318495
申请日：2002-12-11
IPC分类号： H01L021/00 , H01L021/8244 , H01L029/76 , H01L031/062 , H01L031/119
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
摘要翻译： 形成SRAM单元装置的方法包括以下步骤。 形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为形成在平面绝缘体上的平行岛的硅层。 通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到 到共同的身体层。 形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。 然后，连接FET晶体管以形成SRAM单元。
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公开(公告)号：US20040135188A1
公开(公告)日：2004-07-15
申请号：US10341187
申请日：2003-01-13
发明人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
IPC分类号： H01L027/108
CPC分类号： H01L29/945 , H01L27/10861 , H01L27/10894 , H01L29/66181
摘要： A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.
摘要翻译： 基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。 该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。
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公开(公告)号：US20040048441A1
公开(公告)日：2004-03-11
申请号：US10241225
申请日：2002-09-10
发明人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Kenneth T. Settlemyer JR. , Helmut Horst Tews
IPC分类号： H01L021/20
CPC分类号： H01L27/1087
摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.
摘要翻译： 在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在 下部。
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6.发明申请METHOD OF IMPROVING GATE ACTIVATION BY EMPLOYING ATOMIC OXYGEN ENHANCED OXIDATION 失效通过使用原子氧增强氧化来改善门控活化的方法公开(公告)号：US20030010972A1
公开(公告)日：2003-01-16
申请号：US09905233
申请日：2001-07-13
IPC分类号： H01L027/01 , H01L031/0392 , H01L029/06
CPC分类号： H01L21/28035 , H01L21/32105 , H01L29/4916
摘要： The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The thermal budget of the inventive sidewall oxidation process is reduced one or two orders of magnitude over conventional prior art sidewall oxidation processes by utilizing atomic oxygen as the oxidizing ambient. The present invention also provides Si-based MIS transistors having a gate conductor having grain sizes of about 0.1, preferably 0.05, nullm or less.
摘要翻译： 本发明提供一种制备Si基金属 - 绝缘体半导体（MIS）晶体管的方法，其通过降低侧壁氧化工艺的热量预算来防止栅极导体的多晶晶粒变得明显更大。 通过利用原子氧作为氧化环境，本发明的侧壁氧化过程的热预算比常规现有技术的侧壁氧化过程减少一到两个数量级。 本发明还提供具有晶体尺寸为约0.1μm，优选0.05μm或更小的栅极导体的Si基MIS晶体管。
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7.发明申请Gate metal recess for oxidation protection and parasitic capacitance reduction 失效栅极金属凹槽用于氧化保护和寄生电容降低公开(公告)号：US20040150056A1
公开(公告)日：2004-08-05
申请号：US10355726
申请日：2003-01-31
发明人： Haining Yang , Ramachandra Divakaruni , Oleg Gluschenkov , Rajeev Malik , Hongwen Yan , Ravikumar Ramachandran
IPC分类号： H01L029/76 , H01L029/94
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/76838
摘要： A method of fabricating a semiconductor device having a dielectric structure on which a gate stack having a gate stack surface is formed, the gate stack having one or more gate metal layers comprising a gate metal, wherein the gate metal is recessed from the gate stack surface by a chemical etch, is provided. The method includes oxidizing the gate metal of the gate stack selectively to form a smooth side wall on the gate stack, and depositing a gate spacer to the gate stack.
摘要翻译： 一种制造具有电介质结构的半导体器件的方法，其上形成具有栅叠层表面的栅极叠层，所述栅叠层具有一个或多个包含栅极金属的栅极金属层，其中栅极金属从栅叠层表面凹陷 通过化学蚀刻。 所述方法包括选择性地氧化栅极堆叠的栅极金属，以在栅极堆叠上形成平滑的侧壁，以及将栅极间隔物沉积到栅极叠层。
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8.发明申请HIGH PERFORMANCE LOGIC AND HIGH DENSITY EMBEDDED DRAM WITH BORDERLESS CONTACT AND ANTISPACER 失效高性能逻辑和高密度嵌入式DRAM与无边界接触和防抖公开(公告)号：US20030224573A1
公开(公告)日：2003-12-04
申请号：US10160540
申请日：2002-05-31
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
IPC分类号： H01L029/76
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit such as a memory chip with embedded logic or a logic array or processor with imbedded large cache memory in which all significant sources of incompatibility between array transistors and high performance logic transistors are resolved. The integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, F, and memory cell areas or 8-12 F2 and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel length of 0.7F or less, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译： 诸如具有嵌入式逻辑的存储器芯片或具有嵌入式大型高速缓冲存储器的逻辑阵列或处理器的集成电路，其中解决了阵列晶体管和高性能逻辑晶体管之间的所有重要的不兼容的源。 集成电路包括具有由最小光刻特征尺寸F和存储单元面积分离的阵列晶体管的存储单元，以及由扩散阻挡层封装的8-12F 2和未硅化的金属位线，而高性能逻辑晶体管可形成在 相同的芯片不损害性能，包括0.7F或更小的有效沟道长度，用于低源极/漏极接触电阻的硅化触点，用于控制短沟道效应的延伸和晕轮注入以及具有高杂质浓度的双功函数半导体栅极，以及 相应地薄的耗尽层厚度与现有技术的栅介质厚度相当。 该结构通过使用掩模或抗间隔物（优选易于平坦化的材料）开发不同材料的厚/高结构来实现，并且使用平坦化为不同材料的结构的高度的类似掩模以使基板和栅极注入分离 在逻辑晶体管中。
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9.发明申请A 3-D MICROELECTRONIC STRUCTURE INCLUDING A VERTICAL THERMAL NITRIDE MASK 审中-公开一个三维微电子结构，包括一个垂直的硝酸盐掩蔽公开(公告)号：US20030107111A1
公开(公告)日：2003-06-12
申请号：US10013797
申请日：2001-12-10
发明人： Oleg Gluschenkov , Michael P. Chudzik , Rajarao Jammy , Christopher C. Parks , Kenneth T. Settlemyer JR. , Radhika Srinivasan , Kathryn H. Varian
IPC分类号： H01L023/58
CPC分类号： H01L27/1087 , H01L21/3185
摘要： A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.
摘要翻译： 提供了一种3D微电子结构，其包括其中存在至少一个开口的基底，所述至少一个开口具有延伸到公共底壁的侧壁; 以及存在于开口的每个侧壁的至少上部的热氮化物层。 还提供了一种用于制造上述3D微电子结构的方法。 具体地，该方法包括在形成于基板中的开口的每个侧壁的至少上部选择性地形成热氮化物层的步骤。
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公开(公告)号：US20030032272A1
公开(公告)日：2003-02-13
申请号：US09928759
申请日：2001-08-13
发明人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
IPC分类号： H01L021/3205
CPC分类号： H01L21/823481 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
摘要翻译： 提供了一种形成JOI结构的方法，该方法允许减少源极/漏极结漏电流和电容。 在本发明的方法中，在源极/漏极区域之下形成绝缘体层，但不在沟道区域下方。 在本发明中，在形成栅极叠层区域并使包围栅极堆叠区域的半导体表面凹陷之后形成绝缘体层，随后沉积诸如多晶硅的导电材料，以及任选的沉积源极/漏极扩散形成。
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