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公开(公告)号：US11916099B2
公开(公告)日：2024-02-27
申请号：US17341489
申请日：2021-06-08
发明人： Takashi Ando , Reinaldo Vega , David Wolpert , Cheng Chi , Praneet Adusumilli
CPC分类号： H01L28/60 , H01L29/516
摘要： A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.
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公开(公告)号：US11707002B2
公开(公告)日：2023-07-18
申请号：US17233968
申请日：2021-04-19
发明人： Jianshi Tang , Takashi Ando , Reinaldo Vega , Praneet Adusumilli
CPC分类号： H10N70/063 , H10B63/80 , H10N70/24 , H10N70/826 , H10N70/8416
摘要： Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.
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公开(公告)号：US20220416157A1
公开(公告)日：2022-12-29
申请号：US17449515
申请日：2021-09-30
发明人： Kangguo Cheng , Carl Radens , Juntao Li , Ruilong Xie , Praneet Adusumilli , Oscar van der Straten , Alexander Reznicek , Zuoguang Liu , Arthur Gasasira
IPC分类号： H01L45/00
摘要： A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.
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4.发明申请公开(公告)号：US20220190167A1
公开(公告)日：2022-06-16
申请号：US17118752
申请日：2020-12-11
发明人： Takashi Ando , REINALDO VEGA , Cheng Chi , Praneet Adusumilli
IPC分类号： H01L29/78 , H01L29/66 , H01L27/092 , H01L27/07
摘要： A negative capacitance field effect transistor (NCFET) device is provided. The NCFET device includes a substrate, and a transistor stack structure formed on the substrate. The nanosheet stack structure includes a PFET region and an NFET region, the PFET region including a pWF metal layer stack and the NFET region including a nWF metal layer stack. The NCFET device also includes a dielectric interfacial layer formed on the transistor stack structure, the dielectric interfacial layer including metal induced oxygen vacancies, and the dielectric interfacial layer formed on a portion of the transistor stack structure. The NCFET device also includes a top electrode formed on the dielectric interfacial layer.
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公开(公告)号：US20220173312A1
公开(公告)日：2022-06-02
申请号：US17106286
申请日：2020-11-30
发明人： Praneet Adusumilli , Anirban Chandra , Takashi Ando , Cheng Chi , Reinaldo Vega
IPC分类号： H01L45/00
摘要： A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.
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公开(公告)号：US20220158091A1
公开(公告)日：2022-05-19
申请号：US16952203
申请日：2020-11-19
发明人： Takashi Ando , Praneet Adusumilli , REINALDO VEGA , Cheng Chi
摘要： A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode, a first resistive structure in contact with the first electrode, a dielectric layer in contact with the first resistive structure, and a second resistive structure in contact with the dielectric layer. The second resistive structure includes a resistive material layer and a high work function metal core. The ReRAM device also includes a second electrode in contact with the second resistive structure.
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公开(公告)号：US11177436B2
公开(公告)日：2021-11-16
申请号：US16394305
申请日：2019-04-25
发明人： Takashi Ando , Praneet Adusumilli , Jianshi Tang , Reinaldo Vega
摘要： A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.
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公开(公告)号：US20210305093A1
公开(公告)日：2021-09-30
申请号：US16832167
申请日：2020-03-27
IPC分类号： H01L21/768 , H01L21/8238 , H01L29/78 , H01L29/66 , H01L29/40 , H01L29/423 , H01L27/092
摘要： A semiconductor structure is provided including a gate cut region in which the contact trench size has been optimized to increase local interconnect connectivity. The semiconductor structure can include at least one gate structure located laterally adjacent to a gate cut region. At least one metal-containing contact structure is located in the gate cut region, wherein the at least one at least one metal-containing contact structure is confined by a pair of gate dielectric spacers, wherein a first gate dielectric spacer of the pair of gate dielectric spacers has a first width and is located laterally adjacent to the at least one gate structure, and a second gate dielectric spacer of the pair of gate dielectric spacers has a second width and is located laterally adjacent to the at least one metal-containing contact structure, wherein the first width is greater than the second width.
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公开(公告)号：US11011697B2
公开(公告)日：2021-05-18
申请号：US16746558
申请日：2020-01-17
摘要： A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.
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公开(公告)号：US10916471B2
公开(公告)日：2021-02-09
申请号：US16669643
申请日：2019-10-31
IPC分类号： H01L21/8238 , H01L21/768 , H01L23/535 , H01L27/092 , H01L23/525 , H01L23/532 , H01L21/285
摘要： A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.
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