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公开(公告)号：US10979337B2
公开(公告)日：2021-04-13
申请号：US16775804
申请日：2020-01-29
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger
IPC分类号： G06F15/17 , H04L12/701 , H04L12/721 , G06F15/173
摘要： A method, system and computer program product are disclosed for routing data packet in a computing system comprising a multidimensional torus compute node network including a multitude of compute nodes, and an I/O node network including a plurality of I/O nodes. In one embodiment, the method comprises assigning to each of the data packets a destination address identifying one of the compute nodes; providing each of the data packets with a toio value; routing the data packets through the compute node network to the destination addresses of the data packets; and when each of the data packets reaches the destination address assigned to said each data packet, routing said each data packet to one of the I/O nodes if the toio value of said each data packet is a specified value. In one embodiment, each of the data packets is also provided with an ioreturn value used to route the data packets through the compute node network.
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公开(公告)号：US20190199653A1
公开(公告)日：2019-06-27
申请号：US15855447
申请日：2017-12-27
发明人： Sameer Kumar , Philip Heidelberger , Dong Chen , Yutaka Sugawara , Robert M. Senger , Burkhard Steinmacher-Burow
IPC分类号： H04L12/861 , H04L12/879 , H04L29/08 , G06F9/54
摘要： A shared memory maintained by sender processes stores a sequence number counter per destination process. A sender process increments the sequence number counter in the shared memory in sending a message to a destination process. The sender process sends a data packet comprising the message and at least a sequence number specified by the sequence number counter. All of the sender processes share a sequence number counter per destination process, each of the sender processes incrementing the sequence number counter in sending a respective message. Receiver processes run on the hardware processor, each of the receiver processes maintaining a local memory counter on the memory, the local memory counter associated with a sending node. The local memory counter stores a sequence number of a message received from the sending node. The receiver process delivers incoming data packets ordered by sequence numbers of the data packets.
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公开(公告)号：US09954760B2
公开(公告)日：2018-04-24
申请号：US15420588
申请日：2017-01-31
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger
IPC分类号： G06F15/173 , H04L12/701 , H04L12/721
CPC分类号： H04L45/00 , G06F15/17387 , H04L45/06
摘要： A method, system and computer program product are disclosed for routing data packet in a computing system comprising a multidimensional torus compute node network including a multitude of compute nodes, and an I/O node network including a plurality of I/O nodes. In one embodiment, the method comprises assigning to each of the data packets a destination address identifying one of the compute nodes; providing each of the data packets with a toio value; routing the data packets through the compute node network to the destination addresses of the data packets; and when each of the data packets reaches the destination address assigned to said each data packet, routing said each data packet to one of the I/O nodes if the toio value of said each data packet is a specified value. In one embodiment, each of the data packets is also provided with an ioreturn value used to route the data packets through the compute node network.
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公开(公告)号：US09910783B2
公开(公告)日：2018-03-06
申请号：US15424688
申请日：2017-02-03
IPC分类号： G06F12/08 , G06F12/0888 , G06F12/126
CPC分类号： G06F12/0888 , G06F12/126 , G06F2212/1024 , G06F2212/154 , G06F2212/604
摘要： A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.
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公开(公告)号：US20170161200A1
公开(公告)日：2017-06-08
申请号：US15424688
申请日：2017-02-03
IPC分类号： G06F12/0888 , G06F12/126
CPC分类号： G06F12/0888 , G06F12/126 , G06F2212/1024 , G06F2212/154 , G06F2212/604
摘要： A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.
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公开(公告)号：US09501333B2
公开(公告)日：2016-11-22
申请号：US14143783
申请日：2013-12-30
发明人： Daniel Ahn , Luis H. Ceze , Dong Chen Chen , Alan Gara , Philip Heidelberger , Martin Ohmacht
摘要： A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.
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公开(公告)号：US20160011996A1
公开(公告)日：2016-01-14
申请号：US14701371
申请日：2015-04-30
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
摘要翻译： 100 petaflop规模的多千兆高效并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括单个专用集成电路（ASIC）。 ASIC节点通过五维环面网络互连，最优化节点之间的分组通信的吞吐量并最小化等待时间。 网络实现集体网络和提供全局障碍和通知功能的全球异步网络。 集成在节点设计中包括一个基于列表的预取器。 存储系统实现事务存储器，线程级别推测和多重切换缓存，同时提高软错误率，并支持DMA功能，允许并行处理消息传递。
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公开(公告)号：US09218291B2
公开(公告)日：2015-12-22
申请号：US13950371
申请日：2013-07-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/126 , G06F2212/1024 , G06F2212/154 , G06F2212/604
摘要： A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.
摘要翻译： 一种用于在存储器系统中实现存储器层级放置决策的方法，系统和存储器控制器，包括将到达数据直接路由到主存储器系统中，并且将数据或计算结果选择性地注入计算机系统中的处理器高速缓存。 存储器控制器或存储器系统中的处理元件选择性地将数据放置到存储器层级的其他级别中。 注入层次结构的决定可以通过来自输入输出（IO）设备的数据到来自计算或来自存储器内处理元件的指令来触发。
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公开(公告)号：US20150032968A1
公开(公告)日：2015-01-29
申请号：US13950371
申请日：2013-07-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/126 , G06F2212/1024 , G06F2212/154 , G06F2212/604
摘要： A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.
摘要翻译： 一种用于在存储器系统中实现存储器层级放置决策的方法，系统和存储器控制器，包括将到达数据直接路由到主存储器系统中，并且将数据或计算结果选择性地注入计算机系统中的处理器高速缓存。 存储器控制器或存储器系统中的处理元件选择性地将数据放置到存储器层级的其他级别中。 注入层次结构的决定可以通过来自输入输出（IO）设备的数据到来自计算或来自存储器内处理元件的指令来触发。
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公开(公告)号：US20140207987A1
公开(公告)日：2014-07-24
申请号：US14143783
申请日：2013-12-30
发明人： Daniel Ahn , Luis H. Ceze , Dong Chen Chen , Alan Gara , Philip Heidelberger , Martin Ohmacht
IPC分类号： G06F9/52
摘要： A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.
摘要翻译： 多处理器系统支持多种并发模式的推测执行。 投机标识号（ID）从可用数字池中分配给投机线程。 池被分为域，每个域被分配到一种投机模式。 投机模式包括TM，TLS和回滚。 对于中央状态表并使用硬件指针执行ID的分配。 ID用于以高速缓冲存储器中的集合的不同方式写入不同版本的推测结果。
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