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    Reducing aborts caused by a runtime helper called during execution of a transaction block
    2.
    发明授权
    Reducing aborts caused by a runtime helper called during execution of a transaction block 有权
    减少在执行事务块期间调用的运行时帮助程序引起的中止

    公开(公告)号：US09501314B2

    公开(公告)日：2016-11-22

    申请号：US14769739

    申请日：2014-01-21

    Applicant: International Business Machines Corporation

    Inventor： Jose G. Castanos ,  Takuya Nakaike ,  Rei Odaira ,  Peng Wu

    IPC: G06F9/46

    CPC classification number: G06F9/467

    Abstract: A system and method for reducing the number of aborts caused by a runtime helper being called during the execution of a transaction block. When a runtime helper is called during the execution of a transaction block while a program using hardware transactional memory is running, the runtime helper passes ID information indicating the type of runtime helper to an abort handler. When there is an abort caused by a call to a runtime helper, the abort handler responds by acquiring the ID information of the runtime helper that caused the abort, disables the transaction block with respect to a specific type of runtime helper, executes the non-transactional path corresponding to the transaction block, and re-enables the transaction block when predetermined conditions are satisfied.

    Abstract translation: 一种用于减少在执行事务块期间被调用的运行时协助器引起的中止次数的系统和方法。 当在运行硬件事务内存的程序运行期间在执行事务块期间调用运行时帮助程序时，运行时帮助程序将指示运行时助手类型的ID信息传递给中止处理程序。 当通过调用运行时帮助器而导致中止时，中止处理程序通过获取导致中止的运行时协助者的ID信息来响应，禁止关于特定类型的运行时帮助器的事务块， 对应于事务块的事务路径，并且当满足预定条件时重新启用事务块。

    ABORT REDUCING METHOD, ABORT REDUCING APPARATUS, AND ABORT REDUCING PROGRAM
    3.
    发明申请
    ABORT REDUCING METHOD, ABORT REDUCING APPARATUS, AND ABORT REDUCING PROGRAM 有权
    减少方法，减少装置，减少程序

    公开(公告)号：US20160004557A1

    公开(公告)日：2016-01-07

    申请号：US14769739

    申请日：2014-01-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jose G. Castanos ,  Takuya Nakaike ,  Rei Odaira ,  Peng Wu

    IPC: G06F9/46

    CPC classification number: G06F9/467

    Abstract: A system and method for reducing the number of aborts caused by a runtime helper being called during the execution of a transaction block. When a runtime helper is called during the execution of a transaction block while a program using hardware transactional memory is running, the runtime helper passes ID information indicating the type of runtime helper to an abort handler. When there is an abort caused by a call to a runtime helper, the abort handler responds by acquiring the ID information of the runtime helper that caused the abort, disables the transaction block with respect to a specific type of runtime helper, executes the non-transactional path corresponding to the transaction block, and re-enables the transaction block when predetermined conditions are satisfied.

    Abstract translation: 一种用于减少在执行事务块期间被调用的运行时协助器引起的中止次数的系统和方法。 当在运行硬件事务内存的程序运行期间在执行事务块期间调用运行时帮助程序时，运行时帮助程序将指示运行时助手类型的ID信息传递给中止处理程序。 当通过调用运行时帮助器而导致中止时，中止处理程序通过获取导致中止的运行时协助者的ID信息来响应，禁止关于特定类型的运行时帮助器的事务块， 对应于事务块的事务路径，并且当满足预定条件时重新启用事务块。

    Speculative thread execution with hardware transactional memory
    4.
    发明授权
    Speculative thread execution with hardware transactional memory 有权
    使用硬件事务内存的推测线程执行

    公开(公告)号：US08881153B2

    公开(公告)日：2014-11-04

    申请号：US13801943

    申请日：2013-03-13

    Applicant: International Business Machines Corporation

    Inventor： Mark E. Giampapa ,  Thomas M. Gooding ,  Raul E. Silvera ,  Kai-Ting Amy Wang ,  Peng Wu ,  Xiaotong Zhuang

    IPC: G06F9/46 ,  G06F9/40 ,  G06F12/08 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F9/50

    CPC classification number: G06F9/466 ,  G06F9/3842 ,  G06F9/467 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5016 ,  G06F9/52 ,  G06F12/0862

    Abstract: In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted.

    Abstract translation: 在一个实施例中，如果自线程具有多于一个冲突，则自线程的事务被中止并重新启动。 如果自线程只有一个冲突，并且自线程的敌方线程有多个冲突，则自线程的事务被提交。 如果自线程只与敌方线程冲突，敌方线程只与自线程冲突，自线程的密钥优先级高于敌方线程的密钥，则自线程的事务被提交。 如果自线程只与敌方线程相冲突，敌方线程只会与自身线程冲突，自线程的密钥优先级低于敌方线程的密钥，自身线程的事务中止。

    Optimize control-flow convergence on SIMD engine using divergence depth
    5.
    发明授权
    Optimize control-flow convergence on SIMD engine using divergence depth 有权

    公开(公告)号：US10936323B2

    公开(公告)日：2021-03-02

    申请号：US16439210

    申请日：2019-06-12

    Applicant: International Business Machines Corporation

    Inventor： Gheorghe Almasi ,  Jose Moreira ,  Jessica H. Tseng ,  Peng Wu

    IPC: G06F9/40 ,  G06F9/52 ,  G06F15/80 ,  G06F9/38 ,  G06F8/41 ,  G06F9/30 ,  G06F9/32

    Abstract: There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running Single Program Multiple Data code on a Single Instruction Multiple Data machine. The machine runs an instruction stream over input data streams and machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation and updates the lane-PC of each active lane according to targets of the branch operation. An instruction of the instruction stream includes a barrier indicating a convergence point for all lanes to join. In response to a lane reaching a barrier: evaluating whether all lane-PCs are set to a same thread-PC; and if the lane-PCs are not set to the same thread-PC, selecting an active lane from the plurality of lanes; otherwise, incrementing the lane-PCs of all the lanes, and then selecting an active lane from the plurality of lanes.

    Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes
    7.
    发明申请
    Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes 审中-公开
    将处理器内核从线程转换到通道模式，并实现两种模式之间的数据传输

    公开(公告)号：US20160147536A1

    公开(公告)日：2016-05-26

    申请号：US14552145

    申请日：2014-11-24

    Applicant: International Business Machines Corporation

    Inventor： David J. Edelsohn ,  Jose E. Moreira ,  Mauricio J. Serrano ,  Ilie G. Tanase ,  Jessica H. Tseng ,  Peng Wu

    IPC: G06F9/30

    CPC classification number: G06F9/30189 ,  G06F9/3009 ,  G06F9/30123 ,  G06F9/30145

    Abstract: Techniques for switching between two (thread and lane) modes of execution in a dual execution mode processor are provided. In one aspect, a method for executing a single instruction stream having alternating serial regions and parallel regions in a same processor is provided. The method includes the steps of: creating a processor architecture having, for each architected thread of the single instruction stream, one set of thread registers, and N sets of lane registers across N lanes; executing instructions in the serial regions of the single instruction stream in a thread mode against the thread registers; executing instructions in the parallel regions of the single instruction stream in a lane mode against the lane registers; and transitioning execution of the single instruction stream from the thread mode to the lane mode or from the lane mode to the thread mode.

    Abstract translation: 提供了在双执行模式处理器中在两个（线程和通道）执行模式之间切换的技术。 在一个方面，提供了一种在相同处理器中执行具有交替的串行区域和并行区域的单个指令流的方法。 该方法包括以下步骤：创建对于单个指令流的每个架构线程，在N个通道上具有一组线程寄存器和N组通道寄存器的处理器架构; 在针对线程寄存器的线程模式中执行单个指令流的串行区域中的指令; 在相对于车道列表的车道模式中执行单个指令流的并行区域中的指令; 并且将单个指令流的执行从线程模式转换到车道模式或从车道模式转换到线程模式。

    OPTIMIZE CONTROL-FLOW CONVERGENCE ON SIMD ENGINE USING DIVERGENCE DEPTH
    8.
    发明申请
    OPTIMIZE CONTROL-FLOW CONVERGENCE ON SIMD ENGINE USING DIVERGENCE DEPTH 有权
    使用分流深度优化SIMD发动机的控制流合并

    公开(公告)号：US20160062771A1

    公开(公告)日：2016-03-03

    申请号：US14468904

    申请日：2014-08-26

    Applicant: International Business Machines Corporation

    Inventor： Gheorghe Almasi ,  Jose Moreira ,  Jessica H. Tseng ,  Peng Wu

    IPC: G06F9/38 ,  G06F9/45

    CPC classification number: G06F9/3887 ,  G06F8/41 ,  G06F8/443 ,  G06F8/452 ,  G06F8/453 ,  G06F8/458 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/3851 ,  G06F9/3885 ,  G06F15/80 ,  G06F15/8007 ,  G06F15/8023

    Abstract: There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running SPMD (Single Program Multiple Data) code on SIMD (Single Instruction Multiple Data) machine. The machine runs an instruction stream over input data streams. The machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation. The machine updates the lane-PC of each active lane according to targets of the branch operation. The machine selects an active lane and activates only lanes whose lane-PCs match the thread-PC. The machine decrements the lane depth counters of the selected active lanes and updates the lane-PC of each active lane upon the instruction stream reaching a first instruction. The machine assigns the lane-PC of a lane with a largest lane depth counter value to the thread-PC and activates all lanes whose lane-PCs match the thread-PC.

    Abstract translation: 提供了一种在SIMD（单指令多数据）机器上运行SPMD（单程序多数据）代码时选择活动数据流（一个通道）的系统，方法和计算机程序产品。 机器通过输入数据流运行指令流。 在线程PC到达分支操作时，机器增加所有活动通道的车道深度计数器。 机器根据分支操作的目标更新每个活动车道的lane-PC。 机器选择一个活动通道，并仅激活通道PC与线程PC匹配的通道。 当指令流达到第一条指令时，机器递减所选活动通道的车道深度计数器，并更新每个活动车道的车道PC。 机器为线程PC分配具有最大车道深度计数器值的车道的lane-PC，并激活通道PC与线程PC匹配的所有车道。

    OPTIMIZE CONTROL-FLOW CONVERGENCE ON SIMD ENGINE USING DIVERGENCE DEPTH
    10.
    发明申请
    OPTIMIZE CONTROL-FLOW CONVERGENCE ON SIMD ENGINE USING DIVERGENCE DEPTH 审中-公开

    公开(公告)号：US20190294444A1

    公开(公告)日：2019-09-26

    申请号：US16439210

    申请日：2019-06-12

    Applicant: International Business Machines Corporation

    Inventor： Gheorghe Almasi ,  Jose Moreira ,  Jessica H. Tseng ,  Peng Wu

    IPC: G06F9/38 ,  G06F8/41 ,  G06F15/80

    Abstract: There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running Single Program Multiple Data code on a Single Instruction Multiple Data machine. The machine runs an instruction stream over input data streams and machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation and updates the lane-PC of each active lane according to targets of the branch operation. An instruction of the instruction stream includes a barrier indicating a convergence point for all lanes to join. In response to a lane reaching a barrier: evaluating whether all lane-PCs are set to a same thread-PC; and if the lane-PCs are not set to the same thread-PC, selecting an active lane from the plurality of lanes; otherwise, incrementing the lane-PCs of all the lanes, and then selecting an active lane from the plurality of lanes.

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