公开(公告)号：US20180269292A1

公开(公告)日：2018-09-20

申请号：US15982370

申请日：2018-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/812 ,  H01L29/47 ,  H01L29/49 ,  H01L29/51 ,  H01L27/12

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US20170131477A1

公开(公告)日：2017-05-11

申请号：US14933705

申请日：2015-11-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brett CUCCI ,  Paul F. FORTIER ,  Jeffrey P. GAMBINO ,  Robert K. LEIDY ,  Qizhi LIU ,  Richard J. RASSEL

IPC: G02B6/30 ,  G02B6/13

CPC classification number: G02B6/30 ,  G02B6/4243 ,  G02B6/428

Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures for preventing dicing damage on photonics wafers. The structure includes: an optical waveguide structure to optical fiber interface formed on an integrated circuit; and a groove formed in a substrate and which includes a structure preventing a fluid pressure of a dicing operation from damaging the substrate along the groove.

公开(公告)号：US20160146672A1

公开(公告)日：2016-05-26

申请号：US14553203

申请日：2014-11-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qizhi LIU ,  Anthony K. STAMPER ,  Ronald F. WALLER

IPC: G01J5/20 ,  H01L37/00 ,  H01J37/317

CPC classification number: G01J5/20 ,  G01J5/024 ,  G01J2005/202 ,  G01J2005/206 ,  H01J37/3171 ,  H01J2237/31701 ,  H01L37/00

Abstract: A microbolometer device integrated with CMOS and BiCMOS technologies and methods of manufacture are disclosed. The method includes forming a microbolometer unit cell, comprises damaging a portion of a substrate to form a damaged region. The method further includes forming infrared (IR) absorbing material on the damaged region. The method further includes isolating the IR absorbing material by forming a cavity underneath the IR absorbing material.

Abstract translation: 公开了与CMOS和BiCMOS技术以及制造方法集成的微测辐射计装置。 该方法包括形成微量热计单元电池，包括损坏基板的一部分以形成受损区域。 该方法还包括在损伤区域上形成红外（IR）吸收材料。 该方法还包括通过在IR吸收材料下形成空腔来隔离IR吸收材料。

公开(公告)号：US20160093523A1

公开(公告)日：2016-03-31

申请号：US14963530

申请日：2015-12-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. JAFFE ,  Alvin J. JOSEPH ,  Qizhi LIU ,  Anthony K. STAMPER

IPC: H01L21/764

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract translation: 公开了具有下面的气隙的场效应晶体管（FET）和制造方法。 该方法包括在衬底的预定深度处形成非晶层。 该方法还包括在非晶层下方的衬底中形成气隙。 该方法还包括在非晶层和气隙之上的衬底的有源区中形成完全隔离的晶体管。

公开(公告)号：US20160013208A1

公开(公告)日：2016-01-14

申请号：US14864066

申请日：2015-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/41775 ,  H01L21/28052 ,  H01L27/1203 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66848 ,  H01L29/66871 ,  H01L29/7835 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract translation: 公开了可调谐击穿电压RF MESFET和/或MOSFET及其制造方法。 该方法包括在下面的栅极电介质材料上形成第一条线和第二条线。 第二行具有调谐到击穿电压的宽度。 该方法还包括在第一和第二线路的侧壁上形成侧壁间隔物，使得第一和第二线路之间的空间被介电隔离物夹紧。 该方法还包括形成邻近第一线和第二线的外边缘的源极和漏极区域，以及移除至少第二线，以在第二线路的侧壁间隔物之间​​形成开口并暴露下面的栅极电介质材料。 该方法还包括在开口内的下面的栅极电介质材料上沉积材料层，以及形成与栅极结构和源极和漏极区域的接触。

公开(公告)号：US20180323268A1

公开(公告)日：2018-11-08

申请号：US16031371

申请日：2018-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/812 ,  H01L29/47 ,  H01L29/49 ,  H01L29/51 ,  H01L27/12

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US20180226477A1

公开(公告)日：2018-08-09

申请号：US15944018

申请日：2018-04-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/812 ,  H01L29/47 ,  H01L29/49 ,  H01L29/51 ,  H01L27/12

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US20170170056A1

公开(公告)日：2017-06-15

申请号：US15437736

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. JAFFE ,  Alvin J. JOSEPH ,  Qizhi LIU ,  Anthony K. STAMPER

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US20190139819A1

公开(公告)日：2019-05-09

申请号：US16240304

申请日：2019-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. JAFFE ,  Alvin J. JOSEPH ,  Qizhi LIU ,  Anthony K. STAMPER

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/764 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L21/266 ,  H01L21/027

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US20160013290A1

公开(公告)日：2016-01-14

申请号：US14864020

申请日：2015-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC: H01L29/66 ,  H01L23/66

CPC classification number: H01L29/41775 ,  H01L21/28052 ,  H01L27/1203 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66848 ,  H01L29/66871 ,  H01L29/7835 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.