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    Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the transistor
    2.
    发明授权
    Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the transistor 有权
    具有侧壁定义的本征基极到外部基极连接区域的晶体管结构和形成晶体管的方法

    公开(公告)号：US08673726B2

    公开(公告)日：2014-03-18

    申请号：US13762445

    申请日：2013-02-08

    Applicant: International Business Machines Corporation

    Inventor： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

    IPC: H01L21/00

    CPC classification number: H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

    Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

    Abstract translation: 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定的导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

    TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR
    3.
    发明申请
    TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR 有权
    具有侧向定义的内部基极到极端基底连接区域的晶体管结构和形成晶体管的方法

    公开(公告)号：US20130149832A1

    公开(公告)日：2013-06-13

    申请号：US13762445

    申请日：2013-02-08

    Applicant: International Business Machines Corporation

    Inventor： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

    IPC: H01L29/06

    CPC classification number: H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

    Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

    Abstract translation: 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

    Planar cavity MEMS and related structures, methods of manufacture and design structures
    9.
    发明授权
    Planar cavity MEMS and related structures, methods of manufacture and design structures 有权

    公开(公告)号：US11021364B2

    公开(公告)日：2021-06-01

    申请号：US16031132

    申请日：2018-07-10

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Russell T. Herrin ,  Jeffrey C. Maling ,  Anthony K. Stamper

    IPC: B81C1/00 ,  H01L41/113 ,  H01H57/00 ,  H01H1/00

    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

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