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    PHOTORESIST COLLAPSE METHOD FOR FORMING A PHYSICAL UNCLONABLE FUNCTION
    2.
    发明申请
    PHOTORESIST COLLAPSE METHOD FOR FORMING A PHYSICAL UNCLONABLE FUNCTION 有权
    用于形成物理不可靠函数的光电聚焦方法

    公开(公告)号：US20150235964A1

    公开(公告)日：2015-08-20

    申请号：US14181960

    申请日：2014-02-17

    申请人： International Business Machines Corporation

    发明人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H01L23/544 ,  H01L21/3105

    CPC分类号： H01L21/32139 ,  G09C1/00 ,  H01L21/0273 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76885 ,  H01L22/34 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/57 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2224/05097 ,  H04L9/3278 ,  H04L2209/12

    摘要： An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.

    摘要翻译： 有机材料层被光刻图案化以包括线和空间的直线阵列部分。 在一个实施例中，有机材料层可以是利用在有机平坦化层的图案化期间消耗的光致抗蚀剂层进行图案化的有机平坦化层。 有机平面化层在暴露于含卤素气体时的体积膨胀导致线性阵列的部分在随机位置崩溃。 在另一个实施方案中，选择光致抗蚀剂层的高度，使得光致抗蚀剂层的线性阵列部分在机械上不稳定并产生随机光刻胶塌陷。 由于有机材料层的崩溃引起的包括随机修饰的图案被转移到下层中，以产生具有短路或开放的随机电气中断的导电材料线的阵列。 具有随机短路的结构可用作物理不可克隆功能。

    PHYSICAL UNCLONABLE INTERCONNECT FUNCTION ARRAY
    4.
    发明申请
    PHYSICAL UNCLONABLE INTERCONNECT FUNCTION ARRAY 有权
    物理不可变的互连功能阵列

    公开(公告)号：US20150348899A1

    公开(公告)日：2015-12-03

    申请号：US14825303

    申请日：2015-08-13

    申请人： International Business Machines Corporation

    发明人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H01L23/522 ,  H01L23/528

    CPC分类号： H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

    摘要： A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

    摘要翻译： 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

    Clock phase shift detector
    5.
    发明授权
    Clock phase shift detector 有权
    时钟相移检测器

    公开(公告)号：US09077319B2

    公开(公告)日：2015-07-07

    申请号：US14156795

    申请日：2014-01-16

    申请人： International Business Machines Corporation

    发明人： Kai D. Feng ,  Jong-ru Guo ,  Trushil N. Shah ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H03K5/00 ,  H03L7/087

    CPC分类号： H03K5/00 ,  H03L7/087

    摘要： A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

    摘要翻译： 时钟相移检测器电路可以包括接收第一和第二时钟信号的相位检测器，由此相位检测器基于第一和第二时钟信号之间的相位差产生相位信号。 第一积分器耦合到相位检测器，接收相位信号，并产生积分相位信号。 第二积分器接收第一时钟信号并产生积分的第一时钟信号。 比较器耦合到第一和第二积分器，由此比较器接收积分相位信号和集成的第一时钟信号。 然后，比较器可以产生控制信号，该控制信号基于积分相位信号和集成的第一时钟信号之间的幅度比较来检测第一和第二时钟信号的相位差与优化的相位差之间的变化。

    EMBEDDED ON-CHIP SECURITY
    6.
    发明申请
    EMBEDDED ON-CHIP SECURITY 有权
    嵌入式片上安全

    公开(公告)号：US20150084193A1

    公开(公告)日：2015-03-26

    申请号：US14032218

    申请日：2013-09-20

    申请人： International Business Machines Corporation

    发明人： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H01L23/535 ,  H01L23/00 ,  H01L21/768

    CPC分类号： H01L21/76802 ,  G06F21/73 ,  G09C1/00 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/535 ,  H01L23/564 ,  H01L23/57 ,  H01L2924/0002 ,  H03K19/003 ,  H03K19/0948 ,  H04L9/3278 ,  H04L2209/12 ,  H01L2924/00

    摘要： Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification.

    摘要翻译： 本发明的实施例包括一种半导体结构，其包含用于实现物理不可克隆功能（PUF）的线性随机图案化互连结构的后端，用于形成半导体器件的方法以及用于使互连结构实现物理不可克隆功能的电路 。 该方法包括在衬底上形成半导体衬底和介电层。 随机图案化的互连结构形成在电介质层中。 互连结构的随机图案用于实现物理不可克隆功能，并且是在半导体结构的制造期间发生缺陷的结果。 该电路包括n沟道和p沟道金属氧化物半导体场效应晶体管（MOSFET）和随机图案化的互连结构，其作为MOSFET之间的电连接。 MOSFET之间的随机电气连接用于产生用于诸如认证或识别之类目的的唯一密钥。

    CLOCK PHASE SHIFT DETECTOR
    8.
    发明申请
    CLOCK PHASE SHIFT DETECTOR 有权
    时钟相移检测器

    公开(公告)号：US20140159775A1

    公开(公告)日：2014-06-12

    申请号：US14156795

    申请日：2014-01-16

    申请人： International Business Machines Corporation

    发明人： Kai D. Feng ,  Jong-ru Guo ,  Trushill N. Shah ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H03K5/00

    CPC分类号： H03K5/00 ,  H03L7/087

    摘要： A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.

    摘要翻译： 时钟相移检测器电路可以包括接收第一和第二时钟信号的相位检测器，由此相位检测器基于第一和第二时钟信号之间的相位差产生相位信号。 第一积分器耦合到相位检测器，接收相位信号，并产生积分相位信号。 第二积分器接收第一时钟信号并产生积分的第一时钟信号。 比较器耦合到第一和第二积分器，由此比较器接收积分相位信号和集成的第一时钟信号。 然后，比较器可以产生控制信号，该控制信号基于积分相位信号和集成的第一时钟信号之间的幅度比较来检测第一和第二时钟信号的相位差与优化的相位差之间的变化。

    Clock phase shift detector
    9.
    发明授权
    Clock phase shift detector 失效
    时钟相移检测器

    公开(公告)号：US08638124B1

    公开(公告)日：2014-01-28

    申请号：US13707748

    申请日：2012-12-07

    申请人： International Business Machines Corporation

    发明人： Kai D. Feng ,  Jon-ru Guo ,  Trushil N. Shah ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： G01R25/00 ,  H03K5/13

    CPC分类号： G01R25/00 ,  G01R31/31727 ,  G01R31/318552 ,  H03K5/13 ,  H03L7/081 ,  H03L7/085

    摘要： A clock phase shift detector circuit may include a phase detector for generating a phase signal based on a phase difference between first and second clock signals. A current mirror having a first, a second, and a third integrator may be coupled to the phase detector, whereby the first integrator integrates the first clock signal and generates a first voltage, the second integrator integrates the first clock signal and generates a second voltage, and the third integrator integrates the phase signal and generates a third voltage. A first comparator receives the first and the third voltage, and generates a first control signal. A second comparator receives the second and the third voltage, and generates a second control signal. The first and second control signals may detect a change between the phase difference of the first and the second clock signal and an optimized phase difference.

    摘要翻译： 时钟相移检测器电路可以包括相位检测器，用于基于第一和第二时钟信号之间的相位差产生相位信号。 具有第一，第二和第三积分器的电流镜可以耦合到相位检测器，由此第一积分器对第一时钟信号进行积分并产生第一电压，第二积分器对第一时钟信号进行积分并产生第二电压 并且第三积分器对相位信号进行积分并产生第三电压。 第一比较器接收第一和第三电压，并产生第一控制信号。 第二比较器接收第二和第三电压，并产生第二控制信号。 第一和第二控制信号可以检测第一和第二时钟信号的相位差和优化的相位差之间的变化。