公开(公告)号：US06586163B1

公开(公告)日：2003-07-01

申请号：US09587359

申请日：2000-06-02

申请人： Ichiro Okabe ,  Hiroki Arai

发明人： Ichiro Okabe ,  Hiroki Arai

IPC分类号： G03F700

CPC分类号： G03F7/091 ,  G03F7/0045 ,  G03F7/16

摘要： There is described a method of forming a fine pattern aimed at depositing a silicon-nitride-based anti-reflection film which is stable even at high temperature and involves small internal stress. The method is also intended to preventing occurrence of a footing pattern (a rounded corner) in a boundary surface between a photoresist and a substrate at the time of formation of a chemically-amplified positive resist pattern on the anti-reflection film. The method includes the steps of forming a silicon-nitride-based film directly on a substrate or on a substrate by way of another layer; and forming a photoresist directly on the silicon-nitride-based film or on the silicon-nitride-based film by way of another layer. The silicon-nitride-based film is deposited while the temperature at which the substrate is to be situated is set so as to fall within the range of 400 to 700° C., through use of a plasma CVD system. The method further includes a step of depositing a silicon-oxide-based film immediately below the photoresist. The silicon-oxide-based film is deposited while the temperature at which the substrate is to be situated is set so as to fall within the range of 400 to 700° C., through use of a plasma CVD system.

摘要翻译： 描述了一种形成精细图案的方法，其目的在于沉积即使在高温下也是稳定且涉及小的内应力的氮化硅基抗反射膜。 该方法还旨在防止在防反射膜上形成化学放大的正抗蚀剂图案时光致抗蚀剂和基板之间的边界表面中的基脚图案（圆角）的发生。 该方法包括以下步骤：通过另一层直接在衬底或衬底上形成氮化硅基膜; 以及通过另一层在氮化硅基膜或氮化硅基膜上直接形成光致抗蚀剂。 通过使用等离子体CVD系统，将基板的位置的温度设定为400〜700℃的范围，来沉积氮化硅基膜。 该方法还包括在光致抗蚀剂正下方沉积氧化硅基膜的步骤。 通过使用等离子体CVD系统，将基板的位置的温度设定为400〜700℃的范围内，沉积硅氧化物系膜。

公开(公告)号：US06992013B1

公开(公告)日：2006-01-31

申请号：US09597161

申请日：2000-06-20

申请人： Ichiro Okabe ,  Hiroki Arai

发明人： Ichiro Okabe ,  Hiroki Arai

IPC分类号： H01L21/302

CPC分类号： H01L21/02164 ,  G03F7/0045 ,  G03F7/091 ,  G03F7/16 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/316 ,  H01L21/31612

摘要： In a method of forming a fine pattern, a silicon-oxide-based film is formed directly or by way of another layer on a substrate or on an underlying layer. The silicon-oxide-based film is formed such that nitrogen content of the surface thereof assumes a value of 0.1 atm. % or less. A chemically-amplified photoresist layer is formed on the silicon-oxide-based film. A mask pattern of a mask is transferred onto the chemically-amplified photoresist layer upon exposure through the mask. Thus, there is prevented generation of a tapered corner in a portion of a resist pattern in the vicinity of a boundary area between the resist pattern and a substrate.

摘要翻译： 在形成精细图案的方法中，氧化硅基膜直接或通过另一层形成在衬底上或在下层上形成。 形成氧化硅类膜，使得其表面的氮含量为0.1atm。 ％ 或更少。 在氧化硅基膜上形成化学放大型光致抗蚀剂层。 当通过掩模曝光时，掩模的掩模图案被转移到化学放大的光致抗蚀剂层上。 因此，防止在抗蚀剂图案和基板之间的边界区域附近的抗蚀剂图案的一部分中产生锥形角。

公开(公告)号：US09104609B2

公开(公告)日：2015-08-11

申请号：US13846090

申请日：2013-03-18

申请人： Hiroki Arai

发明人： Hiroki Arai

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F1/14 ,  G06F11/20

CPC分类号： G06F11/1402 ,  G06F1/14 ,  G06F11/2038

摘要： The time in the chipset of backup resources is synchronized easily at the system time.An information processing apparatus including: an operational chipset which includes a first Real Time Clock (RTC); a backup chipset which includes a second RTC: a third RTC which times system time; a difference time calculation unit which calculates a difference time between a system time periodically notified of from the first RTC of the operational chipset and the system time which the third RTC times; a holding unit which holds the difference time; a calculation unit which calculates a temporary system time which is set to the second RTC of the backup chipset to which a chipset switching operated, based on the system time of the third RTC and the difference time at the time of the chipset switching; and a configuration unit which sets the temporary system time to the second RTC of the backup chipset.

摘要翻译： 备份资源芯片组的时间在系统时间很容易同步。 一种信息处理设备，包括：操作芯片组，其包括第一实时时钟（RTC）; 包括第二RTC的备用芯片组：第三个RTC，系统时间; 差分时间计算单元，计算从操作芯片组的第一RTC周期性地通知的系统时间与第三RTC时间的系统时间之间的差时间; 保持差时间的保持单元; 计算单元，其基于第三RTC的系统时间和芯片组切换时的差时间，计算设置为进行芯片组切换操作的备用芯片组的第二RTC的临时系统时间; 以及将临时系统时间设置为备用芯片组的第二RTC的配置单元。

公开(公告)号：US20130035440A1

公开(公告)日：2013-02-07

申请号：US13641839

申请日：2011-04-07

申请人： Raita Nishikawa ,  Hiroki Arai ,  Katsuhei Ohnishi

发明人： Raita Nishikawa ,  Hiroki Arai ,  Katsuhei Ohnishi

IPC分类号： C08L81/04 ,  C08K7/14 ,  B29C45/00

CPC分类号： C08L81/02 ,  B29C45/0001 ,  B29K2081/00 ,  C08K7/14 ,  C08L77/12

摘要： To provide a polyarylene sulfide resin composition which contains decreased amount of chlorine, which has a high fluidity and generates small flashes at the time of molding, which has an excellent heat resistance, which can resist heat-processing under the condition of a high temperature, which has moldability at a low mold temperature, a molded article of which has an extremely small change in surface hue before and after reflow. The resin composition is obtained by blending: 100 parts by weight of a polyarylene sulfide resin (A) containing 500 to 2,000 ppm of chlorine and having 10 to 200 Pa·s of melt viscosity, 10 to 100 parts by weight of a liquid crystalline polyester amide resin (B), and 5 to 250 parts by weight of glass fiber (C) containing 100 ppm or less of nitrogen, and having a total chlorine content of 950 ppm or less,

摘要翻译： 本发明提供一种聚酰亚胺硫化物树脂组合物，该组合物在高温下能够耐热处理，具有流动性高，成型时产生小的闪光，具有优异的耐热性， 其在低模具温度下具有成型性，其成型制品在回流之前和之后具有非常小的表面色调变化。 树脂组合物通过以下方法获得：将100重量份含有500-2000ppm氯和10-200Pa·s熔体粘度的聚芳硫醚树脂（A），10至100重量份的液晶聚酯 酰胺树脂（B）和5〜250重量份含有100ppm以下的氮，总氯含量为950ppm以下的玻璃纤维（C）

公开(公告)号：US07825480B2

公开(公告)日：2010-11-02

申请号：US12132610

申请日：2008-06-04

申请人： Hiroki Arai ,  Nobuyuki Shirai ,  Tsuyoshi Kachi

发明人： Hiroki Arai ,  Nobuyuki Shirai ,  Tsuyoshi Kachi

IPC分类号： H01L27/088

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.

摘要翻译： 提高了包括沟槽栅极功率MISFET的半导体器件的特性。 半导体器件包括具有设置有功率MISFET的有源区域的基板和位于有源区域的周向外侧并且设有耐击穿结构的外周区域，由设置在基板上的导电膜形成的图案 具有介于其间的绝缘膜的外周区域，与图案隔离的另一图案，以及电连接到功率MISFET的栅电极并设置在导电膜上的层中的栅电极端子。 图案的导电膜电耦合到栅电极端子，而另一图案的导电膜与栅电极端子电耦合。

公开(公告)号：US20050022737A1

公开(公告)日：2005-02-03

申请号：US10897061

申请日：2004-07-22

申请人： Akira Shimizu ,  Hideaki Fukuda ,  Hiroki Arai ,  Baiei Kawano ,  Takayuki Yamagishi

发明人： Akira Shimizu ,  Hideaki Fukuda ,  Hiroki Arai ,  Baiei Kawano ,  Takayuki Yamagishi

IPC分类号： H01L21/683 ,  C23C16/00 ,  C23C16/458 ,  H01L21/205 ,  H01L21/677 ,  H01L21/68

CPC分类号： C23C16/4585

摘要： A semiconductor-processing apparatus comprises a susceptor and removable placing blocks detachably placed at a periphery of the susceptor for transferring a substrate. Retractable supporting members are provided for detaching/attaching the placing blocks from/to the susceptor.

摘要翻译： 半导体处理装置包括基座和可拆卸地放置在基座周边的可拆卸放置块，用于传送基板。 提供可伸缩的支撑构件用于将放置块从基座分离/附接到基座。

公开(公告)号：US09116689B2

公开(公告)日：2015-08-25

申请号：US13036495

申请日：2011-02-28

申请人： Hiroki Arai

发明人： Hiroki Arai

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/32 ,  Y02D10/24

摘要： An information processing unit includes a processing unit including a plurality of processor cores; and a power consumption reduction device configured to reduce power consumption of the processing unit. The power consumption reduction device measures the loads on threads that are running in the plurality of cores; checks the number of high load threads which are threads in a high load state and the number of low load threads which are threads in a low load state for each core, on the basis of the measuring results; selects, when there exists a core having high load threads whose number is less than a preset threshold on the number of high load threads, the core as a candidate core; and replaces the high load threads existing in the candidate core with the low load threads existing in other cores when the total number of the low load threads in a core other than the candidate core is not less than the number of the high load threads in the candidate core.

摘要翻译： 信息处理单元包括：处理单元，包括多个处理器核; 以及功耗降低装置，被配置为降低处理单元的功耗。 功耗降低装置测量在多个芯中运行的线程上的负载; 基于测量结果，检查处于高负载状态的线程的高负载线数和每个核心处于低负载状态的线程的低负载线程的数量; 当存在具有高负载线程数目大于预设阈值的高负载线程的核心作为候选核心时，选择所述核心作为候选核心; 并且当候选核心之外的核心中的低负载线程的总数不小于所述候选核心中的高负载线程的数量时，用存在于其他核心中的低负载线程替换候选核心中存在的高负载线程 候选人核心。

公开(公告)号：US08852707B2

公开(公告)日：2014-10-07

申请号：US13513771

申请日：2010-12-02

申请人： Raita Nishikawa ,  Tatsuya Kanezuka ,  Hiroki Arai ,  Yoshihito Fukasawa

发明人： Raita Nishikawa ,  Tatsuya Kanezuka ,  Hiroki Arai ,  Yoshihito Fukasawa

IPC分类号： C08L81/02 ,  C08L23/02 ,  B29C45/00 ,  B29C45/14

CPC分类号： B29C45/14 ,  B29C45/0001 ,  C08L23/02 ,  C08L81/02 ,  Y10T428/23 ,  Y10T428/31529 ,  Y10T428/31533 ,  C08L2666/04 ,  C08L33/068

摘要： Provided is a PAS resin composition with which molded articles having excellent high- and low-temperature impact properties can be obtained and which can be highly inhibited from leaving mold deposits when molded and is suitable for use in insert molding. Also provided is an insert-molded article obtained using the resin composition. The PAS-derived resin composition comprises a PAS resin having carboxylic terminal groups and an olefin-derived copolymer, wherein the olefin-derived copolymer comprises units of an α-olefin, a glycidyl ester of an α,β-unsaturated acid, and an acrylic ester as comonomer units, the PAS resin has a number average molecular weight of 1,000-10,000, and the content of the comonomer units derived from the glycidyl ester in the resin composition is 0.08-0.20 mass %, the ratio of the content of the comonomer units derived from the glycidyl ester (mmol/kg) to the amount of the carboxylic terminal groups (mmol/kg) being 0.35-1.00.

摘要翻译： 提供了一种PAS树脂组合物，其可以获得具有优异的高低温冲击性能的模塑制品，并且当模制时可以高度地抑制模具沉积物并且适合用于嵌件成型。 还提供了使用该树脂组合物获得的嵌入成型制品。 PAS衍生的树脂组合物包含具有羧基端基的PAS树脂和烯烃衍生的共聚物，其中所述烯烃衍生的共聚物包含α-烯烃，α和β-不饱和酸的缩水甘油酯和 丙烯酸酯作为共聚单体单元，PAS树脂的数均分子量为1,000〜10,000，树脂组合物中衍生自缩水甘油酯的共聚单体单元的含量为0.08〜0.20质量％ 衍生自缩水甘油酯（mmol / kg）的共聚单体单元与羧基端基（mmol / kg）的量为0.35-1.00。

公开(公告)号：US08546223B2

公开(公告)日：2013-10-01

申请号：US12889343

申请日：2010-09-23

申请人： Hiroki Arai ,  Nobuyuki Shirai ,  Tsuyoshi Kachi

发明人： Hiroki Arai ,  Nobuyuki Shirai ,  Tsuyoshi Kachi

IPC分类号： H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： The characteristics of a semiconductor device including a trench-gate power MISFET are improved. The semiconductor device includes a substrate having an active region where the power MISFET is provided and an outer circumferential region which is located circumferentially outside the active region and where a breakdown resistant structure is provided, a pattern formed of a conductive film provided over the substrate in the outer circumferential region with an insulating film interposed therebetween, another pattern isolated from the pattern, and a gate electrode terminal electrically coupled to the gate electrodes of the power MISFET and provided in a layer over the conductive film. The conductive film of the pattern is electrically coupled to the gate electrode terminal, while the conductive film of another pattern is electrically decoupled from the gate electrode terminal.

摘要翻译： 提高了包括沟槽栅极功率MISFET的半导体器件的特性。 半导体器件包括具有设置有功率MISFET的有源区域的基板和位于有源区域的周向外侧并且设有耐击穿结构的外周区域，由设置在基板上的导电膜形成的图案 具有介于其间的绝缘膜的外周区域，与图案隔离的另一图案，以及电连接到功率MISFET的栅电极并设置在导电膜上的层中的栅电极端子。 图案的导电膜电耦合到栅电极端子，而另一图案的导电膜与栅电极端子电耦合。

公开(公告)号：US20120237714A1

公开(公告)日：2012-09-20

申请号：US13513771

申请日：2010-12-02

申请人： Raita Nishikawa ,  Tatsuya Kanezuka ,  Hiroki Arai ,  Yoshihito Fukasawa

发明人： Raita Nishikawa ,  Tatsuya Kanezuka ,  Hiroki Arai ,  Yoshihito Fukasawa

IPC分类号： C08L81/04 ,  B32B3/08 ,  B32B15/08 ,  B29C45/14

CPC分类号： B29C45/14 ,  B29C45/0001 ,  C08L23/02 ,  C08L81/02 ,  Y10T428/23 ,  Y10T428/31529 ,  Y10T428/31533 ,  C08L2666/04 ,  C08L33/068

摘要： Provided is a PAS resin composition with which molded articles having excellent high- and low-temperature impact properties can be obtained and which can be highly inhibited from leaving mold deposits when molded and is suitable for use in insert molding. Also provided is an insert-molded article obtained using the resin composition. The PAS-derived resin composition comprises a PAS resin having carboxylic terminal groups and an olefin-derived copolymer, wherein the olefin-derived copolymer comprises units of an α-olefin, a glycidyl ester of an α,β-unsaturated acid, and an acrylic ester as comonomer units, the PAS resin has a number average molecular weight of 1,000-10,000, and the content of the comonomer units derived from the glycidyl ester in the resin composition is 0.08-0.20 mass %, the ratio of the amount of the carboxylic terminal groups (mmol/kg) and the content of the comonomer units derived from the glycidyl ester (mmol/kg) being 0.35-1.00.

摘要翻译： 提供了一种PAS树脂组合物，其可以获得具有优异的高低温冲击性能的模塑制品，并且当模制时可以高度地抑制模具沉积物并且适合用于嵌件成型。 还提供了使用该树脂组合物获得的嵌入成型制品。 PAS衍生的树脂组合物包含具有羧基端基的PAS树脂和烯烃衍生的共聚物，其中所述烯烃衍生的共聚物包含α-烯烃，α和β-不饱和酸的缩水甘油酯和 丙烯酸酯作为共聚单体单元，PAS树脂的数均分子量为1,000〜10,000，树脂组合物中由缩水甘油酯衍生的共聚单体单元的含量为0.08〜0.20质量％ 羧酸端基（mmol / kg），衍生自缩水甘油酯的共聚单体单元的含量（mmol / kg）为0.35-1.00。