公开(公告)号：US20160351437A1

公开(公告)日：2016-12-01

申请号：US15112083

申请日：2014-12-29

申请人： Igor PEIDOUS ,  SUNEDISON SEMICONDUCTOR LIMITED

发明人： Igor Peidous ,  Srikanth Kommu ,  Gang Wang ,  Shawn George Thomas

IPC分类号： H01L21/762

CPC分类号： H01L21/76251 ,  H01L21/76254

摘要： A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

摘要翻译： 提供了用于制造SOI结构的高电阻率单晶半导体手柄结构。 手柄结构包括在处理衬底和掩埋氧化物层之间的中间半导体层。 中间半导体层包括多晶，非晶，纳米晶体或单晶结构，并且包括选自Si1-xGex，Si1-xCx，Si1-x-yGexSny，Si1-xy-zGexSnyCz，Ge1-xSnx， IIIA-氮化物，半导体氧化物及其任何组合。

公开(公告)号：US10468294B2

公开(公告)日：2019-11-05

申请号：US16077142

申请日：2017-01-31

申请人： SUNEDISON SEMICONDUCTOR LIMITED ,  Igor Peidous

发明人： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Gang Wang ,  Jeffrey L. Libbert

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/30 ,  H01L21/46 ,  H01L29/04 ,  H01L31/036 ,  H01L21/762 ,  H01L21/02 ,  H01L21/28

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.

公开(公告)号：US07767540B2

公开(公告)日：2010-08-03

申请号：US11567268

申请日：2006-12-06

申请人： Igor Peidous ,  Thorsten Kammler ,  Andy Wei

发明人： Igor Peidous ,  Thorsten Kammler ,  Andy Wei

IPC分类号： H01L21/76

CPC分类号： H01L29/7843 ,  H01L21/26506 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.

摘要翻译： 通过相对于硅层的结晶特性适当地定向沟道长度方向，与常规技术相比，应变硅/碳材料的应力诱导效应可以显着提高。 在一个说明性实施例中，通道可以沿着（100）表面取向沿着<100>方向取向，从而提供大约四分之一的电子迁移率增加。

公开(公告)号：US20100096698A1

公开(公告)日：2010-04-22

申请号：US12644882

申请日：2009-12-22

申请人： Igor Peidous ,  Rohit Pal

发明人： Igor Peidous ,  Rohit Pal

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

摘要： Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer

摘要翻译： 提供了应力增强型MOS晶体管。 提供一种半导体器件，其包括绝缘体上半导体结构，栅极绝缘体层，源极区域，漏极区域和覆盖栅极绝缘体层的导电栅极。 绝缘体上半导体结构包括：衬底，半导体层和设置在衬底和半导体层之间的绝缘层。 半导体层具有第一表面，第二表面和第一区域。 栅极绝缘体层覆盖第一区域，导电栅极覆盖栅极绝缘体层，源区域和漏极区域覆盖在第一表面上，并且包括应变诱导外延层

公开(公告)号：US07534689B2

公开(公告)日：2009-05-19

申请号：US11562209

申请日：2006-11-21

申请人： Rohit Pal ,  Igor Peidous ,  David Brown

发明人： Rohit Pal ,  Igor Peidous ,  David Brown

IPC分类号： H01L21/20

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636

摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

摘要翻译： 提供了一种应力增强型MOS晶体管及其制造方法。 在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。 具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。 沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。 第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由 第三单晶材料。

公开(公告)号：US20080142835A1

公开(公告)日：2008-06-19

申请号：US11611784

申请日：2006-12-15

申请人： Igor Peidous ,  Rohit Pal

发明人： Igor Peidous ,  Rohit Pal

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/78687 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848

摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.

摘要翻译： 提供了一种应力增强型MOS晶体管及其制造方法。 提供了一种绝缘体上半导体结构，其包括具有第一表面的半导体层。 应变诱导外延层被覆盖地沉积在第一表面上，然后可用于产生覆盖在第一表面上的源极区域和漏极区域。

公开(公告)号：US20070032024A1

公开(公告)日：2007-02-08

申请号：US11197046

申请日：2005-08-03

申请人： Igor Peidous ,  Mario Pelella

发明人： Igor Peidous ,  Mario Pelella

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  Y10S438/938

摘要： A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.

摘要翻译： 提供了一种在半导体衬底中及其上制造应力MOS器件的方法。 该方法包括以下步骤：形成覆盖半导体衬底并蚀刻半导体衬底中的第一沟槽和第二沟槽的栅电极，第一沟槽和第二沟槽与栅电极对准形成。 在第一沟槽和第二沟槽中选择性地生长应力诱导材料，并且将导电性确定杂质离子注入到应力诱导材料中，以在第一沟槽中形成源区，在第二沟中形成漏极区。 为了保持在衬底中引起的应力，在离子注入步骤之后，将一层机械硬质材料沉积在应力诱导材料上。

公开(公告)号：US10475695B2

公开(公告)日：2019-11-12

申请号：US15899636

申请日：2018-02-20

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Jeffrey L. Libbert

IPC分类号： H01L21/762 ,  H01L21/304 ,  H01L21/02 ,  H01L21/761 ,  H01L29/06 ,  H01L21/322 ,  H01L21/265

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

公开(公告)号：US20180233420A1

公开(公告)日：2018-08-16

申请号：US15893055

申请日：2018-02-09

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Rapoport ,  Srikanth Kommu ,  Igor Peidous ,  Gang Wang ,  Jeffrey L. Libbert

IPC分类号： H01L21/66 ,  H01L23/66

CPC分类号： H01L22/14 ,  G01R31/2648 ,  H01L22/20 ,  H01L23/66 ,  H01L27/12

摘要： Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

公开(公告)号：US09768056B2

公开(公告)日：2017-09-19

申请号：US14524693

申请日：2014-10-27

申请人： SunEdison Semiconductor Limited (UEN201334164H)

发明人： Igor Peidous ,  Illaria Katia Marianna Pellicano

IPC分类号： H01L21/02 ,  H01L21/762

CPC分类号： H01L21/76251 ,  H01L21/02238 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262

摘要： A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.