公开(公告)号：US5267136A

公开(公告)日：1993-11-30

申请号：US790270

申请日：1991-11-12

申请人： Ikuro Suga ,  Masato Koyama

发明人： Ikuro Suga ,  Masato Koyama

IPC分类号： G05F1/56 ,  G05F1/563 ,  H02M3/07 ,  H02M3/28 ,  H02M3/335

CPC分类号： H02M3/285 ,  G05F1/563 ,  H02M3/07 ,  H02M3/33507 ,  Y10T307/675 ,  Y10T307/707

摘要： A DC-DC converter for outputting dc voltage whose peak value is higher than an input dc voltage value and high-frequency voltage corresponding to a command value is superimposed. An insulated switching power supply 27 and a series regulator 26 are connected in parallel to a dc power supply 1. The insulated switching power supply 27 generates output voltage V.sub.2 having a certain level, and the series regulator 26, output voltage V.sub.1 whose voltage varies depending on a command value (command voltage varying at a high frequency). Then, the sum of the output voltages V.sub.1 and V.sub.2 is fed to the load 9.

摘要翻译： 用于输出其峰值高于输入直流电压值的直流电压和对应于指令值的高频电压的DC-DC转换器。 绝缘开关电源27和串联调节器26并联连接到直流电源1.绝缘开关电源27产生具有一定电平的输出电压V2，串联调节器26，其电压变化的输出电压V1 根据指令值（高频变化的指令电压）。 然后，输出电压V1和V2的和被馈送到负载9。

公开(公告)号：US20130234088A1

公开(公告)日：2013-09-12

申请号：US13728552

申请日：2012-12-27

申请人： Yoshifumi Nishi ,  Takao Marukame ,  Takayuki Ishikawa ,  Masato Koyama

发明人： Yoshifumi Nishi ,  Takao Marukame ,  Takayuki Ishikawa ,  Masato Koyama

IPC分类号： H01L45/00

CPC分类号： H01L45/14 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/16

摘要： According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.

摘要翻译： 根据实施例，半导体器件包括第一和第二忆阻器。 第一忆阻器包括由第一材料制成的第一电极，由第二材料制成的第二电极和布置在第一和第二电极之间的第一电阻切换膜。 第一电阻开关膜连接到第一和第二电极。 第二忆阻器包括由第三材料制成的第三电极，由第二材料制成的第四电极和布置在第三和第四电极之间的第二电阻切换膜。 第二电阻开关膜连接到第三和第四电极。 第一材料的功函数小于第二材料的功函数。 第三种材料的功函数大于第二种材料的功函数。

公开(公告)号：US08053300B2

公开(公告)日：2011-11-08

申请号：US11841817

申请日：2007-08-20

申请人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

发明人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属 栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分 的第一电介质面向第一金属栅电极。

公开(公告)号：US20100171184A1

公开(公告)日：2010-07-08

申请号：US12654490

申请日：2009-12-22

申请人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

发明人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属 栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分 的第一电介质面向第一金属栅电极。

公开(公告)号：US07745888B2

公开(公告)日：2010-06-29

申请号：US12232078

申请日：2008-09-10

申请人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

发明人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

IPC分类号： H01L29/76

CPC分类号： H01L21/823842

摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

摘要翻译： 半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例 膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

公开(公告)号：US07718521B2

公开(公告)日：2010-05-18

申请号：US12133605

申请日：2008-06-05

申请人： Masato Koyama ,  Akira Nishiyama ,  Yoshinori Tsuchiya ,  Reika Ichihara

发明人： Masato Koyama ,  Akira Nishiyama ,  Yoshinori Tsuchiya ,  Reika Ichihara

IPC分类号： H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.

摘要翻译： 公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。

公开(公告)号：US20100032765A1

公开(公告)日：2010-02-11

申请号：US12549298

申请日：2009-08-27

申请人： Yoshinori TSUCHIYA ,  Masato Koyama

发明人： Yoshinori TSUCHIYA ,  Masato Koyama

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L29/4958 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665

摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

公开(公告)号：US07646072B2

公开(公告)日：2010-01-12

申请号：US12320280

申请日：2009-01-22

申请人： Yuuichi Kamimuta ,  Akira Nishiyama ,  Yasushi Nakasaki ,  Tsunehiro Ino ,  Masato Koyama

发明人： Yuuichi Kamimuta ,  Akira Nishiyama ,  Yasushi Nakasaki ,  Tsunehiro Ino ,  Masato Koyama

IPC分类号： H01L29/78

CPC分类号： H01L27/11521 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

公开(公告)号：US20090267159A1

公开(公告)日：2009-10-29

申请号：US12388965

申请日：2009-02-19

申请人： Kosuke Tstsumura ,  Masakazu Goto ,  Reika Ichihara ,  Masato Koyama ,  Shigeru Kawanaka ,  Kazuaki Nakajima

发明人： Kosuke Tstsumura ,  Masakazu Goto ,  Reika Ichihara ,  Masato Koyama ,  Shigeru Kawanaka ,  Kazuaki Nakajima

IPC分类号： H01L27/092

CPC分类号： H01L21/823828 ,  H01L21/823842 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的p沟道MIS晶体管，形成在衬底上的第一栅极电介质的p沟道晶体管和形成在第一电介质上的第一栅极电极层，以及n沟道 形成在衬底上的MIS晶体管，所述n沟道晶体管具有形成在衬底上的第二栅极电介质和形成在第二电介质上的第二栅极电极层。 与第一栅极电介质接触的第一栅极电极层的底层和与第二栅极电介质接触的第二栅电极层的底层具有相同的取向和相同的组成，包括Ta和C，以及摩尔比 的Ta与总计C和Ta（Ta /（Ta + C））大于0.5。

公开(公告)号：US20090263950A1

公开(公告)日：2009-10-22

申请号：US12491984

申请日：2009-06-25

申请人： Masato Koyama ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Reika Ichihara ,  Katsuyuki Sekine

发明人： Masato Koyama ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Reika Ichihara ,  Katsuyuki Sekine

IPC分类号： H01L21/336

CPC分类号： H01L27/092 ,  H01L21/28097 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.

摘要翻译： 半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。 第一和第二绝缘层分别具有第一和第二区域。 第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜​​厚度方向上为0.3nm的范围内。 第一和第二区域中的每一个包括浓度为1×10 20 cm -3或更高至1×10 22 cm -3或更小的铝原子。