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公开(公告)号：US08370704B2
公开(公告)日：2013-02-05
申请号：US12381194
申请日：2009-03-09
IPC分类号： H03M13/00
摘要： Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.
摘要翻译： 描述了可以通过电缆延长传输速率的技术。 可以使用多条电缆来提高传输速率。 每个电缆应用的传输标准可以是以太网背板标准，例如IEEE 802.3ap（2007）。 在通过电缆传输之前，可以将数据分配给虚拟通道。 在通过电缆传输之前，可以对每个虚拟通道应用前向纠错。 可以通过单个虚拟通道协商前向纠错，然后应用于所有虚拟通道。
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公开(公告)号：US20100229067A1
公开(公告)日：2010-09-09
申请号：US12381194
申请日：2009-03-09
摘要： Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.
摘要翻译： 描述了可以通过电缆延长传输速率的技术。 可以使用多条电缆来提高传输速率。 每个电缆应用的传输标准可以是以太网背板标准，如IEEE 802.3ap（2007）。 在通过电缆传输之前，可以将数据分配给虚拟通道。 在通过电缆传输之前，可以对每个虚拟通道应用前向纠错。 可以通过单个虚拟通道协商前向纠错，然后应用于所有虚拟通道。
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3.发明授权Manually-operated continuity/shorts test probe for bare interconnection packages 失效手动操作连续性/短路测试探针，用于裸互连封装
公开(公告)号：US5256975A
公开(公告)日：1993-10-26
申请号：US891632
申请日：1992-06-01
IPC分类号： G01R31/28 , G01R31/312 , G01R31/02
CPC分类号： G01R31/2805 , G01R31/312
摘要： A hand-held test probe is employed which uses a capacitance measuring circuit to measure capacitance as the probe is scanned along a pattern of conductors (pads or pins) at a steady rate. The capacitance measurement is stored in a memory during the scan, then maximums are detected in the stored data, corresponding to the conductor pattern. If a particular conductor has a short or a break in continuity, its capacitance will be more or less than it should be. The detected maximums are compared with recorded values for a known-good printed wiring board for this scan pattern. If the comparison shows a difference greater than a selected threshold, an error is indicated for this pin location. The known-good is scanned in a "learn" mode, in which the capacitance values are stored for each scan, identified by scan number.
摘要翻译： 采用手持测试探头，当探头沿着导体（焊盘或引脚）的图案以稳定的速率扫描时，使用电容测量电路来测量电容。 电容测量在扫描期间存储在存储器中，然后在存储的数据中检测最大值，对应于导体图案。 如果特定导体的连续性短或断裂，其电容将大于或小于应该的电容。 将检测到的最大值与用于该扫描图案的已知良好的印刷线路板的记录值进行比较。 如果比较显示大于所选阈值的差异，则会针对该引脚位置指示错误。 已知功能以“学习”模式进行扫描，其中通过扫描号识别每个扫描的电容值。
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4.发明申请公开(公告)号：US20180026917A1
公开(公告)日：2018-01-25
申请号：US15218681
申请日：2016-07-25
IPC分类号： H04L12/935
CPC分类号： H04L49/3054
摘要： Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.
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5.发明申请TECHNOLOGIES FOR EXCHANGING HOST LOSS AND FORWARD ERROR CORRECTION CAPABILITIES ON A 25G ETHERNET LINK 审中-公开在25G以太网链路上交换主机损失和前向纠错能力的技术公开(公告)号：US20160099795A1
公开(公告)日：2016-04-07
申请号：US14580731
申请日：2014-12-23
申请人： Kent C. Lusted , Adee O. Ran , Richard I. Mellitz
发明人： Kent C. Lusted , Adee O. Ran , Richard I. Mellitz
CPC分类号： H04L1/0041 , G06F11/10 , H04L1/0009 , H04L1/0023
摘要： Technologies for capabilities exchange include a network port logic having a communication link coupled to a remote link partner. The port logic transmits local host loss information to the link partner and receives remote host loss information from the link partner. The port logic may communicate the host loss information via an autonegotiation base page, an autonegotiation next page, or a PMD control frame. The port logic determines total channel loss based on the local host loss, the remote host loss, and cable loss. The port logic may bring the communication link up without forward error correction (FEC) if the total channel loss is less than a FEC limit, may bring the link up with FEC if the total loss is less than a specification limit, or may not bring the link up if the total channel loss is above the specification limit. Other embodiments are described and claimed.
摘要翻译： 用于能力交换的技术包括具有耦合到远程链路伙伴的通信链路的网络端口逻辑。 端口逻辑将本地主机丢失信息传输到链路伙伴，并从链路伙伴接收远程主机丢失信息。 端口逻辑可以经由自动协商基页，自动协商下一页或PMD控制帧来传送主机丢失信息。 端口逻辑基于本地主机丢失，远程主机丢失和电缆丢失来确定总信道丢失。 如果总信道损失小于FEC限制，则端口逻辑可以使通信链路上升而不进行前向纠错（FEC），如果总损耗小于规范限制，则可以使链路成为FEC，否则可能不带 如果总频道损失高于规格限制，则链接。 描述和要求保护其他实施例。
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6.发明授权
公开(公告)号：US5596283A
公开(公告)日：1997-01-21
申请号：US579038
申请日：1995-12-19
CPC分类号： G01R31/2808
摘要： Electrical test method and apparatus for performing the method. The method operates to determine an electrical characteristic of a node (2) disposed upon a surface of a substrate (3), such as a printed wiring board (PWB). The method includes a first step of providing relative motion between a probe (1) and the surface of the PWB. A second step measures the electrical characteristic during a time that there is relative motion between the probe and the surface of the PWB. In one embodiment of the invention the step of measuring measures capacitance while in another embodiment of the invention the step of measuring measures charge capacity. The step of providing relative motion, in one embodiment of the invention, includes the steps of maintaining the PWB stationary while linearly translating the probe over the surface. In another embodiment of the invention the step of providing relative motion includes the steps of maintaining the probe stationary while moving the PWB.
摘要翻译： 用于执行该方法的电测试方法和装置。 该方法用于确定设置在诸如印刷线路板（PWB）的基板（3）的表面上的节点（2）的电特性。 该方法包括在探针（1）和PWB的表面之间提供相对运动的第一步骤。 在探针与PWB表面之间存在相对运动的时间内，第二步测量电气特性。 在本发明的一个实施例中，测量电容的步骤，而在本发明的另一个实施例中，测量充电容量的步骤。 在本发明的一个实施例中提供相对运动的步骤包括以下步骤：在探针在表面上线性平移的同时维持PWB的稳定。 在本发明的另一个实施例中，提供相对运动的步骤包括在移动PWB的同时保持探针静止的步骤。
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公开(公告)号：US06421391B1
公开(公告)日：2002-07-16
申请号：US08935909
申请日：1997-09-22
申请人： Richard I. Mellitz
发明人： Richard I. Mellitz
IPC分类号： H04B300
CPC分类号： H04L7/0008
摘要： A transmission line for a clock input for a digital device. In the prior art, a clock signal was fed to a digital device on a transmission line. It was found that, when the clock frequency was doubled, the clock pulses received by the device became unacceptable. The invention lengthened the transmission line, rather than shortening it, and thereby removed the unacceptable features of the clock pulses.
摘要翻译： 用于数字设备的时钟输入的传输线。 在现有技术中，时钟信号被馈送到传输线上的数字设备。 已经发现，当时钟频率加倍时，由器件接收的时钟脉冲变得不可接受。 本发明延长了传输线，而不是缩短传输线，从而消除了时钟脉冲的不可接受的特征。
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8.发明授权
公开(公告)号：US5498965A
公开(公告)日：1996-03-12
申请号：US167381
申请日：1993-12-15
申请人： Richard I. Mellitz
发明人： Richard I. Mellitz
CPC分类号： G01R31/2813 , G01R27/04 , G01R27/06 , G01R31/2822
摘要： Method for determining the characteristic impedance of a transmission line on a printed wiring board using time domain reflectometry. The method involves selecting a driving point in time, selecting an undisturbed interval, measuring voltage at predetermined time intervals across the undisturbed interval, determining from the measured voltages a curve representative of such voltages, and determining the voltage on the representative curve at the driving point. The characteristic impedance of the transmission line under test, denoted by Z.sub.0, is obtained by using the "driving point" of the transmission line as the reference plane for the impedance measurements.
摘要翻译： 使用时域反射法确定印刷电路板上的传输线的特性阻抗的方法。 该方法包括选择时间上的驱动点，选择未受干扰的间隔，在未受干扰的间隔内以预定时间间隔测量电压，根据测量的电压确定表示这种电压的曲线，以及确定驱动点上代表性曲线上的电压 。 通过使用传输线的“驱动点”作为阻抗测量的参考平面，获得被测传输线路的特征阻抗，由Z0表示。
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公开(公告)号：US07076401B2
公开(公告)日：2006-07-11
申请号：US10134390
申请日：2002-04-30
申请人： Richard I. Mellitz
发明人： Richard I. Mellitz
IPC分类号： G04F10/00
CPC分类号： G01R29/26
摘要： A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.
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10.发明授权Electronic circuit board including a second circuit board attached there to to provide an area of increased circuit density 失效电子电路板包括附接到其上的第二电路板，以提供增加电路密度的区域
公开(公告)号：US5825630A
公开(公告)日：1998-10-20
申请号：US744964
申请日：1996-11-07
CPC分类号： H05K1/141 , H05K7/023 , H05K2201/10333 , H05K2201/10689 , H05K3/323 , H05K3/3436 , H05K3/368
摘要： A computer baseboard providing localized support for high pin count, high density components. The baseboard includes a first circuit board capable of supporting low pin count electrical components. The first circuit board has a surface onto which the low pin count electrical components are mounted, and an area to which a second, smaller, circuit board is connected in a parallel arrangement with the first circuit board. The second circuit board has a first surface onto which high pin count electrical components are mounted, and a second surface physically and electrically connected to the area on said first substrate. The first and second circuit boards together provide support for electrical components having higher pin counts and densities than the first circuit board can support individually, such as high performance microprocessors and chipsets. The first circuit board may be a low circuit density substrate while the second circuit board is a high circuit density substrate or multiple substrate layer board. Additionally, the second circuit board can be constructed of materials with better electrical characteristics, such as Cyanate Ester or other material having a low relative permeability, providing an advantage in meeting the tight timing characteristics of new, high performance microprocessors and chipsets.
摘要翻译： 电脑底板为高引脚数，高密度元件提供本地化支持。 该基板包括能够支持低引脚数的电气部件的第一电路板。 第一电路板具有安装有低引脚数电气部件的表面和与第一电路板并联连接的第二较小电路板的区域。 第二电路板具有安装有高引脚数电气部件的第一表面和与第一基板上的区域物理和电连接的第二表面。 第一和第二电路板一起为具有比第一电路板可以单独支持的更高的引脚数和密度的电部件提供支持，例如高性能微处理器和芯片组。 第一电路板可以是低电路密度衬底，而第二电路板是高电路密度衬底或多个衬底层板。 此外，第二电路板可以由具有更好电气特性的材料构成，例如氰酸酯或具有低相对磁导率的其它材料，提供了满足新的高性能微处理器和芯片组的紧密定时特性的优点。
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